Patents by Inventor Mark G. Fernandes

Mark G. Fernandes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6136678
    Abstract: A method for processing a conductive layer, such as a doped polysilicon layer (14) of a gate stack, provides a degas step after precleaning to reduce particle count and defectivity. The conductive layer is provided on a substrate (10), e.g., a silicon wafer. The substrate (10) and conductive layer are subjected to an elevated temperature, under a vacuum, whereby certain species are liberated. The substrate having the conductive layer formed thereon is then removed from the chamber, and moved to a second, separate chamber, in which a second conductive layer (20) is deposited. By switching chambers, the liberated species are largely prevented from contributing to particle count at the interface between the conductive layers. Alternatively, the second conductive layer is formed in the same chamber, provided that the liberated species are removed from the chamber prior to deposition of the second conductive layer.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: October 24, 2000
    Assignee: Motorola, Inc.
    Inventors: Olubunmi Adetutu, James D. Hayden, Chitra Subramanian, Archana Redkar, Anthony Mark Miscione, Mark G. Fernandes
  • Patent number: 5317185
    Abstract: A semiconductor device has structures to reduced stress notching effects in conductive lines. In one form, the semiconductor device includes a semiconductor die which has a plurality of active conductive lines thereon. The plurality of conductive lines collectively has a first and a second outside edge. In close proximity to each of the first and the second outside edges is a stress reducing line. Each of the stress reducing lines is a non-active structure (in other words does not transmit signals) and functions to reduce stress concentrations on the plurality of active conductive lines which are imposed by overlying insulating and passivation layers. As a result of weakened stress concentrations, the amount of stress notching in the active conductive lines is reduced.
    Type: Grant
    Filed: February 18, 1992
    Date of Patent: May 31, 1994
    Assignee: Motorola, Inc.
    Inventors: Mark G. Fernandes, Hisao Kawasaki
  • Patent number: 5310626
    Abstract: A method for forming a patterned layer of material begins by providing a substrate (12). A device layer (14) is formed overlying the substrate (12). A layer (16) is formed over the device layer (14). Layer (16) is further characterized as being an inorganic dielectric material, such as a plasma enhanced silicon nitride (PEN) material. A mask (18) is positioned adjacent the layer (16). Ultra-violet (UV) light (20) is selectively exposed to the layer (16) through the mask (18). Exposure from the UV light (20) forms exposed regions (16b) and unexposed regions (16a) of the layer (16). The UV light (20) alters an atomic bonding energy of hydrogen atoms within the exposed regions (16b) while not altering unexposed regions (16a). The layer (16) is exposed to an etchant which etches the exposed regions (16b) and unexposed regions (16a) at different rates. The etching forms a patterned layer from the layer ( 16) which may be used as a masking layer.
    Type: Grant
    Filed: March 1, 1993
    Date of Patent: May 10, 1994
    Assignee: Motorola, Inc.
    Inventors: Mark G. Fernandes, Stanley M. Filipiak, Jeffrey T. Wetzel