Abstract: A process for etching silicon wafers using a caustic etchant in the form of an aqueous solution comprising water, a hydroxide ion source, and a chelating agent. The process produces silicon wafers substantially free from diffused metal ions.

Abstract: A dressing apparatus for dressing a polishing pad includes a dressing member engageable with the polishing pad. The dressing apparatus is adapted to change the amount of force exerted by the dressing member on the polishing pad as the dressing member moves radially along the polishing pad. A controller for controlling the dressing apparatus has pre-programmed recipes that are selectable based on the radial profile of a measured polished wafer.

Abstract: A system for polishing a semiconductor wafer. The system includes a polishing apparatus having a rotatable polishing pad for polishing the wafer. A dressing apparatus is mounted adjacent the polishing pad for dressing the polishing pad. The dressing apparatus includes a dressing member engageable with the polishing pad. A cleaning apparatus is mounted adjacent the polishing pad for removing particulate and chemicals from the polishing pad. The system includes a controller for controlling the dressing apparatus and the cleaning apparatus.

Abstract: A system for polishing a semiconductor wafer. The system includes a polishing apparatus having a rotatable polishing pad for polishing the wafer. A dressing apparatus is mounted adjacent the polishing pad for dressing the polishing pad. The dressing apparatus includes a dressing member engageable with the polishing pad. A cleaning apparatus is mounted adjacent the polishing pad for removing particulate and chemicals from the polishing pad. The system includes a controller for controlling the dressing apparatus and the cleaning apparatus.

Abstract: A process for etching silicon wafers using a caustic etchant in the form of an aqueous solution comprising water, a hydroxide ion source, and a chelating agent. The process produces silicon wafers substantially free from diffused metal ions.

Abstract: A process for etching silicon wafers using a caustic etchant in the form of an aqueous solution comprising water and a source of hydroxide ions and generally characterized by a lower concentration of water and/or higher concentration of source of hydroxide ions. In accordance with another embodiment, the caustic etchant includes a salt additive. The process produces silicon wafers with improved surface characteristics such as flatness and nanotopography.

Abstract: The process relates to a process for nucleating and growing oxygen precipitates in a silicon wafer. The process includes subjecting a wafer having a non-uniform concentration of crystal lattice vacancies with the concentration of vacancies in the bulk layer being greater than the concentration of vacancies in the surface layer to a non-isothermal heat treatment to form of a denuded zone in the surface layer and to cause the formation and stabilization of oxygen precipitates having an effective radial size 0.5 nm to 30 nm in the bulk layer. The process optionally includes subjecting the stabilized wafer to a high temperature thermal process (e.g. epitaxial deposition, rapid thermal oxidation, rapid thermal nitridation and etc.) at temperatures in the range of 1000° C. to 1275° C. without causing the dissolution of the stabilized oxygen precipitates.

Abstract: A wafer carrier which supports at least one wafer, during a process in which material is deposited on the wafer from chemical vapor in a reactor, includes a base having an inner curved surface extending from a first lateral edge of the base to a second lateral edge of the base. Slots in the inner surface of the base extending generally continuously from the first lateral edge to the second lateral edge are defined by a bottom wall and opposing side walls. The slots may each receive at least a portion of a thin, outwardly facing edge of the wafer for holding the wafer in an upright position. The bottom wall of the slot closely conforms to the predetermined shape of the portion of the outwardly facing peripheral edge of the wafer to inhibit the entry of vapor between the base and the outwardly facing edge of the wafer and the formation of material bridges between the wafer and the carrier by deposition of the material from the chemical vapor.