Patents by Inventor Mark Gaertner

Mark Gaertner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11243887
    Abstract: In accordance with one implementation, a method for mitigating cache transfer time entails reading data into memory from at least two consecutive elliptical data tracks in a main store region of data storage and writing the data read from the at least two consecutive elliptical data tracks to a spiral data track within a cache storage region.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: February 8, 2022
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Andrew Michael Kowles, Xiong Liu, Mark Gaertner, Kai Yang, WenXiang Xie, Jiangnan Lin
  • Publication number: 20200192806
    Abstract: In accordance with one implementation, a method for mitigating cache transfer time entails reading data into memory from at least two consecutive elliptical data tracks in a main store region of data storage and writing the data read from the at least two consecutive elliptical data tracks to a spiral data track within a cache storage region.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Inventors: Andrew Michael KOWLES, Xiong LIU, Mark GAERTNER, Kai YANG, WenXiang XIE, Jiangnan LIN
  • Patent number: 10579533
    Abstract: In accordance with one implementation, a method for mitigating cache transfer time entails reading data into memory from at least two consecutive elliptical data tracks in a main store region of data storage and writing the data read from the at least two consecutive elliptical data tracks to a spiral data track within a cache storage region.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 3, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Andrew Michael Kowles, Xiong Liu, Mark Gaertner, Kai Yang, WenXiang Xie, Jiangnan Lin
  • Patent number: 10580468
    Abstract: In accordance with one implementation, a method for reducing cache service time includes determining an access time parameter associated with movement of a read/write head to an access location for each of a plurality of contiguous cache storage segments and dynamically selecting one of the plurality of contiguous cache storage segments to store data based on the determined access time parameter.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 3, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Andrew Michael Kowles, Mark Gaertner, Xiong Liu, WenXiang Xie, Kai Yang, Jiangnan Lin
  • Patent number: 10310923
    Abstract: Systems and methods are disclosed for probabilistic aging command sorting, including adjusting an execution order for a command based on a probability of the command reaching a time out threshold. Various example embodiments are directed to selecting a command for execution from a queue of commands awaiting execution, in which the commands have non-uniform attributes influencing their selection and a time limit within which to execute them. In some embodiments, an apparatus may comprise a circuit configured to calculate a first estimated access time to execute a selected command from a command queue, modify the first estimated access time based on a probability of the selected command reaching a time-out age threshold to determine a time out-adjusted access time, and execute the selected command in an order based on the time out-adjusted access time.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: June 4, 2019
    Assignee: Seagate Technology LLC
    Inventors: Jeffrey Vincent DeRosa, Jon David Trantham, Mark Gaertner
  • Publication number: 20190103146
    Abstract: In accordance with one implementation, a method for reducing cache service time includes determining an access time parameter associated with movement of a read/write head to an access location for each of a plurality of contiguous cache storage segments and dynamically selecting one of the plurality of contiguous cache storage segments to store data based on the determined access time parameter.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Andrew Michael Kowles, Mark Gaertner, Xiong Liu, WenXiang Xie, Kai Yang, Jiangnan Lin
  • Publication number: 20190102307
    Abstract: In accordance with one implementation, a method for mitigating cache transfer time entails reading data into memory from at least two consecutive elliptical data tracks in a main store region of data storage and writing the data read from the at least two consecutive elliptical data tracks to a spiral data track within a cache storage region.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Andrew Michael Kowles, Xiong Liu, Mark Gaertner, Kai Yang, WenXiang Xie, Jiangnan Lin
  • Patent number: 10180792
    Abstract: Data storage devices may store selected data received from a data source to a buffer memory. The selected data may be copied from the buffer to a non-volatile memory configured for sequential storage. The selected data may then be copied from the buffer to a solid state memory, such as dynamic random access memory. The selected data may be copied from the solid state memory to a main store, such as a magnetic disc memory. If the selected data cannot be found in the solid state memory, the selected data in the non-volatile memory can be copied to the main store.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: January 15, 2019
    Assignee: Seagate Technology LLC
    Inventors: Mark Gaertner, James D Sawin
  • Patent number: 9552252
    Abstract: Certain exemplary aspects of the present disclosure are directed towards methods and apparatuses in which logic circuitry generates an error detection code based on user data received from a host, and further generates a first set of check bits, to be written to the non-volatile memory circuit in conjunction with the user data, by combining the error detection code with a hashed data address of the user data. In some embodiments, the check bits associated with the user data providing verification that the user data was written in the appropriate physical block address of the non-volatile memory circuit.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: January 24, 2017
    Assignee: Seagate Technology LLC
    Inventors: Jon D. Trantham, Brian T. Edgar, Mark Gaertner, Bruce Buch
  • Patent number: 9396062
    Abstract: A multi-dimensional recording (MDR) system may include a group based coding circuit (GBCC) which can implement error correcting codes via outer codes. The GBCC can implement outer codes, including interleaving outer codes, in MDR systems where inner codewords include multiple memory groupings. The multiple memory groupings may be across different structural divisions within a data storage medium; or could be across multiple different data storage mediums.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: July 19, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Deepak Sridhara, William Radich, Ara Patapoutian, Timothy R Feldman, Mark Gaertner
  • Publication number: 20160055053
    Abstract: Certain exemplary aspects of the present disclosure are directed towards methods and apparatuses in which logic circuitry generates an error detection code based on user data received from a host, and further generates a first set of check bits, to be written to the non-volatile memory circuit in conjunction with the user data, by combining the error detection code with a hashed data address of the user data. In some embodiments, the check bits associated with the user data providing verification that the user data was written in the appropriate physical block address of the non-volatile memory circuit.
    Type: Application
    Filed: August 25, 2014
    Publication date: February 25, 2016
    Inventors: Jon D. Trantham, Brian T. Edgar, Mark Gaertner, Bruce Buch
  • Patent number: 9244860
    Abstract: A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: January 26, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Mark Gaertner, Mark Alan Heath
  • Publication number: 20150169466
    Abstract: A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.
    Type: Application
    Filed: February 27, 2015
    Publication date: June 18, 2015
    Inventors: Mark Gaertner, Mark Alan Heath
  • Patent number: 8996842
    Abstract: A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: March 31, 2015
    Assignee: Seagate Technology LLC
    Inventors: Mark Gaertner, Mark Alan Heath
  • Patent number: 8214589
    Abstract: Data storage systems are provided. Some embodiments of data storage systems include a storage device controller and a plurality of storage devices. The plurality of storage devices are illustratively in a redundancy scheme and the storage device controller receives from the plurality of storage devices a plurality of symbols. In one embodiment, each of the plurality of symbols is representative of data in the redundancy scheme, and the storage device controller verifies the consistency of the redundancy scheme based at least in part on the plurality of symbols.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: July 3, 2012
    Assignee: Seagate Technology LLC
    Inventors: Michael Miller, Mark Gaertner
  • Publication number: 20120151179
    Abstract: A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 14, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Mark Gaertner, Mark Heath
  • Patent number: 7490261
    Abstract: The present invention is a method of recovering data in a system that stores data in identifiable storage segments. The method includes scanning at least one storage segment for a read error. The method also includes performing a read recovery operation in an attempt to recover a read error. The method logs recovered read errors as a function of the read recovery operation.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: February 10, 2009
    Assignee: Seagate Technology LLC
    Inventors: Mark Gaertner, Xiaoying Li, David A. Anderson
  • Publication number: 20060277441
    Abstract: A unified debug system with multiple user-configurable trace volumes is disclosed, including embodiments as a system, a method, and a computer-readable medium. Embodiments of the present invention provide more robust and flexible solutions for introducing configurable trace volumes to firmware, allowing a user to specify firmware system configurations for trace buffers, trace frames, and trace volumes, and offer other advantages over the prior art. One embodiment of the present invention pertains to a system that includes a firmware component comprising firmware, and a firmware interface communicatively connected to the firmware component. The firmware includes a plurality of trace volumes for storing a plurality of trace entries. The trace volumes are user-configurable through the firmware interface. The plurality of trace volumes includes first, second and third trace volumes. The first trace volume includes storing at least some of the trace entries to a trace buffer in a first volatile memory component.
    Type: Application
    Filed: June 2, 2005
    Publication date: December 7, 2006
    Applicant: Seagate Technology LLC
    Inventors: Brian Edgar, Mark Gaertner, Bhooshan Thakar
  • Publication number: 20060075202
    Abstract: A data storage device mirrors data on a data storage medium. The multiple instances of data are synchronized in order to optimize performance of the reading and writing, and the integrity of the data. Preferably, a data storage device is allowed to defer writing multiple copies of data until a more advantageous time.
    Type: Application
    Filed: November 18, 2005
    Publication date: April 6, 2006
    Applicant: Seagate Technology LLC
    Inventors: Mark Gaertner, Luke Friendshuh, Stephen Cornaby
  • Publication number: 20060005069
    Abstract: A method and a system is provided for increasing reliability of data stored in storage segments by increasing redundancy data and by permitting user data to fit around defective locations in the storage segment. User data is compressed and reserved for a portion of a storage segment having a data size corresponding to an uncompressed size of the user data. The compressed user data is written to the reserved portion of the storage segment and a pad byte pattern is written to any remaining portion of the reserved portion of the storage segment. The remaining portion of the reserved portion of the storage segment is designated as unused.
    Type: Application
    Filed: July 1, 2004
    Publication date: January 5, 2006
    Inventor: Mark Gaertner