Patents by Inventor Mark Gerald Rosario Pinlac

Mark Gerald Rosario Pinlac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Structure and method for stabilizing leads in wire-bonded semiconductor devices
    Patent number: 9824959
    Abstract: A semiconductor device having a leadframe including a pad (101) surrounded by elongated leads (110) spaced from the pad by a gap (113) and extending to a frame, the pad and the leads having a first thickness (115) and a first and an opposite and parallel second surface; the leads having a first portion (112) of first thickness near the gap and a second portion (111) of first thickness near the frame, and a zone (114) of reduced second thickness (116) between the first and second portions; the second surface (112a) of the first lead portions is coplanar with the second surface (111a) of the second portions. A semiconductor chip (220) with a terminal is attached the pad. A metallic wire connection (230) from the terminal to an adjacent lead includes a stitch bond (232) attached to the first surface of the lead.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: November 21, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dolores Babaran Milo, Mark Gerald Rosario Pinlac, Bobby Johns Lansangan Villacarlos, Jerry Gomez Cayabyab, Juan Carlo Aro Rimando
  • STRUCTURE AND METHOD FOR STABILIZING LEADS IN WIRE-BONDED SEMICONDUCTOR DEVICES
    Publication number: 20170278776
    Abstract: A semiconductor device having a leadframe including a pad (101) surrounded by elongated leads (110) spaced from the pad by a gap (113) and extending to a frame, the pad and the leads having a first thickness (115) and a first and an opposite and parallel second surface; the leads having a first portion (112) of first thickness near the gap and a second portion (111) of first thickness near the frame, and a zone (114) of reduced second thickness (116) between the first and second portions; the second surface (112a) of the first lead portions is coplanar with the second surface (111a) of the second portions. A semiconductor chip (220) with a terminal is attached the pad. A metallic wire connection (230) from the terminal to an adjacent lead includes a stitch bond (232) attached to the first surface of the lead.
    Type: Application
    Filed: March 23, 2016
    Publication date: September 28, 2017
    Inventors: Dolores Babaran Milo, Mark Gerald Rosario Pinlac, Bobby Johns Lansangan Villacarlos, Jerry Gomez Cayabyab, Juan Carlo Aro Rimando
  • Nonleaded package and leadframe strip and method
    Patent number: 9184120
    Abstract: A nonleaded IC package, such as a QFN, including an encapsulation block having at least one generally flat lateral sidewall surface; and a plurality of leads, each terminating in a generally chair-shaped flat surface that is flush with the generally flat lateral sidewall surface.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: November 10, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dolores Parobrob Babaran, Mark Gerald Rosario Pinlac, Ramil Alfonso Viluan