Patents by Inventor Mark Gerber
Mark Gerber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11969386Abstract: A patient slider device configured to move a patient from a first bed surface to a second bed surface positioned adjacent thereto. The patient slider device includes a frame, a bed engagement assembly and a patient pulling assembly. The bed engagement assembly includes a bumper with the bumper being adjustable relative to the frame. The patient pulling assembly includes a winch assembly, preferably positioned proximate a lower end of the frame, and a sheet engaging clamp assembly. The sheet engaging clamp assembly includes a base member and a locking member structurally configured to clamp a sheet therebetween.Type: GrantFiled: December 22, 2022Date of Patent: April 30, 2024Assignees: Grand Valley State University, Spectrum Health Innovations, LLCInventors: Andrew Heuerman, Eric VanMiddendorp, Michael Czechowskyj, Jason Barr, Mark C Celmer, Vaughn Gerber, Dylan DiGiovanni, Michael Matusiak, Taylor Rieckhoff, Dan Scheske, Justin Dykstra, Ashley Meitz, Garrett Goodwin, Colin Jack, Taylor Sims, Benjamin Vander Wal, John Farris, Chris Pung, Dan Switzer
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Publication number: 20240112978Abstract: An electronic package is provided. The electronic package includes an insulating carrier, a first conductive layer, and an electronic component. The first conductive layer is disposed over the insulating carrier. The electronic component is disposed over the first conductive layer and electrically connected to the first conductive layer, wherein the insulating carrier is configured to dissipate heat from the electronic component to a second side of the insulating carrier opposite to a first side facing the electronic component.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Vikas GUPTA, Mark GERBER
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Patent number: 11862587Abstract: A semiconductor package structure and a method of manufacturing the semiconductor package structure are disclosed. The semiconductor package structure includes a first semiconductor device having an active surface, a redistribution structure in electrical connection with the first semiconductor device, and a second semiconductor device bonded to the active surface of the first semiconductor device, and disposed between the first semiconductor device and the redistribution structure.Type: GrantFiled: July 23, 2020Date of Patent: January 2, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Mark Gerber
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Publication number: 20230123962Abstract: The present disclosure provides an antenna device. The antenna device includes a dielectric element including a first region and a second region, a first antenna disposed on the first region, and a second antenna disposed on the second region. The first antenna and the second antenna are configured to operate in different frequencies. The first antenna and the second antenna are misaligned in directions perpendicular and parallel to a surface of the dielectric element on which the first antenna or the second antenna is disposed.Type: ApplicationFiled: October 15, 2021Publication date: April 20, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Mark GERBER
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Publication number: 20220359425Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.Type: ApplicationFiled: May 24, 2022Publication date: November 10, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Chiang SHIH, Hung-Yi LIN, Meng-Wei HSIEH, Yu Sheng CHANG, Hsiu-Chi LIU, Mark GERBER
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Patent number: 11342282Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.Type: GrantFiled: February 21, 2020Date of Patent: May 24, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Chiang Shih, Hung-Yi Lin, Meng-Wei Hsieh, Yu Sheng Chang, Hsiu-Chi Liu, Mark Gerber
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Patent number: 11146234Abstract: An electrical device includes an electronic component, a membrane and a cover. The electronic component has a first surface and a second surface opposite to the first surface. The electronic component has a cavity extending from the first surface of the electronic component into the electronic component. The membrane is disposed within the cavity of the electronic component. The cover is disposed on the first surface of the electronic component.Type: GrantFiled: June 17, 2019Date of Patent: October 12, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Mark Gerber
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Publication number: 20210265280Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.Type: ApplicationFiled: February 21, 2020Publication date: August 26, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Chiang SHIH, Hung-Yi LIN, Meng-Wei HSIEH, Yu Sheng CHANG, Hsiu-Chi LIU, Mark GERBER
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Publication number: 20210246472Abstract: Methods for increasing targeted genome editing by down-regulating proteins involved in cytosolic DNA sensing pathways.Type: ApplicationFiled: August 20, 2019Publication date: August 12, 2021Inventors: Nathan Zenser, Dmitry Malkov, Mark A. Gerber, Jill Ward
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Publication number: 20210028134Abstract: A semiconductor package structure and a method of manufacturing the semiconductor package structure are disclosed. The semiconductor package structure includes a first semiconductor device having an active surface, a redistribution structure in electrical connection with the first semiconductor device, and a second semiconductor device bonded to the active surface of the first semiconductor device, and disposed between the first semiconductor device and the redistribution structure.Type: ApplicationFiled: July 23, 2020Publication date: January 28, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Mark GERBER
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Publication number: 20190393859Abstract: An electrical device includes an electronic component, a membrane and a cover. The electronic component has a first surface and a second surface opposite to the first surface. The electronic component has a cavity extending from the first surface of the electronic component into the electronic component. The membrane is disposed within the cavity of the electronic component. The cover is disposed on the first surface of the electronic component.Type: ApplicationFiled: June 17, 2019Publication date: December 26, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Mark GERBER
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Patent number: 10177099Abstract: A semiconductor package structure includes a substrate, a first semiconductor device, a first encapsulant and a second encapsulant. The substrate has a first coefficient of thermal expansion CTE1. The first semiconductor device is disposed adjacent to a first surface of the substrate. The first encapsulant is disposed on the first surface of the substrate, and covers at least a portion of the first semiconductor device. The first encapsulant has a second coefficient of thermal expansion CTE2. The second encapsulant is disposed on a second surface of the substrate and has a third coefficient of thermal expansion CTE3. A difference between CTE1 and CTE2 is substantially equal to a difference between CTE1 and CTE3.Type: GrantFiled: April 7, 2017Date of Patent: January 8, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Mark Gerber, Rich Rice, Bradford Factor
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Patent number: 9929072Abstract: A semiconductor device has a semiconductor chip having a first surface with metallized terminals and a parallel second surface. A frame of insulating material adheres to at the sidewalls of the chip. The frame has a first surface planar with the first chip surface and a parallel second surface planar with the second chip surface. The first frame surface includes one or more embedded metallic fiducials extending from the first surface to the insulating material. At least one film of sputtered metal extends from the terminals across the surface of the polymeric layer to the fiducials. The film is patterned to form extended contact pads over the frame and rerouting traces between the chip terminals and the extended contact pads. The film adheres to the surfaces.Type: GrantFiled: December 22, 2015Date of Patent: March 27, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Mark A. Gerber
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Publication number: 20170294389Abstract: A semiconductor package structure includes a substrate, a first semiconductor device, a first encapsulant and a second encapsulant. The substrate has a first coefficient of thermal expansion CTE1. The first semiconductor device is disposed adjacent to a first surface of the substrate. The first encapsulant is disposed on the first surface of the substrate, and covers at least a portion of the first semiconductor device. The first encapsulant has a second coefficient of thermal expansion CTE2. The second encapsulant is disposed on a second surface of the substrate and has a third coefficient of thermal expansion CTE3. A difference between CTE1 and CTE2 is substantially equal to a difference between CTE1 and CTE3.Type: ApplicationFiled: April 7, 2017Publication date: October 12, 2017Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Bradford FACTOR, Rich RICE, Mark GERBER
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Publication number: 20160111349Abstract: A semiconductor device has a semiconductor chip having a first surface with metallized terminals and a parallel second surface. A frame of insulating material adheres to at the sidewalls of the chip. The frame has a first surface planar with the first chip surface and a parallel second surface planar with the second chip surface. The first frame surface includes one or more embedded metallic fiducials extending from the first surface to the insulating material. At least one film of sputtered metal extends from the terminals across the surface of the polymeric layer to the fiducials. The film is patterned to form extended contact pads over the frame and rerouting traces between the chip terminals and the extended contact pads. The film adheres to the surfaces.Type: ApplicationFiled: December 22, 2015Publication date: April 21, 2016Inventor: Mark A. Gerber
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Patent number: 9257341Abstract: A method for fabricating packaged semiconductor devices; attaching a batch-sized metallic grid with openings onto an adhesive tape having an insulating clear core covered by a layer of UV-releasable adhesive, the openings sized larger than a semiconductor chip; attaching a semiconductor chip onto the tape of each window, the chip terminals facing the adhesive surface; laminating insulating material of low coefficient of thermal expansion to fill gaps between each chip and respective grid; turning over assembly to place a carrier under backside of chips and lamination and to remove the tape; plasma-cleaning the assembly front side and sputtering uniform at least one metal layer across the assembly; optionally plating metal layers; and patterning the metal layers to form rerouting traces and extended contact pads for assembly.Type: GrantFiled: July 1, 2014Date of Patent: February 9, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Mark A. Gerber
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Publication number: 20150371963Abstract: A semiconductor device has semiconductor chip assembled on a substrate. The substrate has a first surface including conductive traces, which have a first length and a first width, the first width being uniform along the first length, and further a pitch to respective adjacent traces. The semiconductor chip has a second surface including contact pads; the second surface faces the first surface spaced apart by a gap. A conductive pillar contacts each contact pad; the pillar includes a core and a solder body, which connects the core to the respective trace across the gap. The pillar core has a non-circular cross section of a second width and a second length greater than the second width and greater than the first width.Type: ApplicationFiled: August 28, 2015Publication date: December 24, 2015Inventors: Abram M. Castro, Mark A. Gerber
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Patent number: 9129955Abstract: A semiconductor chip (102) assembled on a substrate (101). The substrate has a first surface (101a) including conductive traces (110), which have a first length (111) and a first width (112), the first width being uniform along the first length, and further a pitch (114) to respective adjacent traces. The semiconductor chip has a second surface (102a) including contact pads (121); the second surface faces the first surface spaced apart by a gap (130). A conductive pillar (140) contacts each contact pad; the pillar includes a metal core (141) and a solder body (142), which connects the core to the respective trace across the gap. The pillar core (141) has an oblong cross section of a second width (151) and a second length (152) greater than the second width. Trace pitch (141) is equal to or smaller than twice the second width (151). The trace pitch is equal to or smaller than the second length (152).Type: GrantFiled: July 15, 2009Date of Patent: September 8, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abram M. Castro, Mark A. Gerber
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Publication number: 20150008566Abstract: A method for fabricating packaged semiconductor devices in panel format; placing a panel-sized metallic grid with openings on an adhesive tape (292); attaching semiconductor chips—coated with a polymer layer having windows for chip terminals —face-down onto the tape (293); laminating low CTE insulating material to fill gaps between chips and grid (294); turning over assembly to place carrier under backside of chips and lamination and to remove tape (295); plasma-cleaning assembly front side, sputtering uniform metal layer across assembly (296); optionally plating metal layer (297); and patterning sputtered layer to form rerouting traces and extended contact pads for assembly (298).Type: ApplicationFiled: July 1, 2014Publication date: January 8, 2015Inventors: Mark A. Gerber, Mutsumi Masumoto, Kenji Masumoto, Anindya Poddar, Kengo Aoya, Masamitsu Matsuura, Takeshi Onogami
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Publication number: 20150008583Abstract: A method for fabricating packaged semiconductor devices; attaching a batch-sized metallic grid with openings onto an adhesive tape having an insulating clear core covered by a layer of UV-releasable adhesive, the openings sized larger than a semiconductor chip; attaching a semiconductor chip onto the tape of each window, the chip terminals facing the adhesive surface; laminating insulating material of low coefficient of thermal expansion to fill gaps between each chip and respective grid; turning over assembly to place a carrier under backside of chips and lamination and to remove the tape; plasma-cleaning the assembly front side and sputtering uniform at least one metal layer across the assembly; optionally plating metal layers; and patterning the metal layers to form rerouting traces and extended contact pads for assembly.Type: ApplicationFiled: July 1, 2014Publication date: January 8, 2015Inventor: Mark A. Gerber