Patents by Inventor Mark Griswold
Mark Griswold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250244430Abstract: Systems and methods for radiofrequency (RF) pulse design are provided. A method includes defining a target slice profile across a slice dimension and simulating a first echo having a first slice profile generated in response to a first one or more RF pulses. The method also includes simulating a second echo having a second slice profile generated in response to a second one or more RF pulses. The method further includes determining pulse parameters of at least one RF pulse for acquiring MRI data from the imaging target by reducing a cost function. The cost function includes a comparison term that calculates a difference between the first slice profile and the second slice profile and a target term that calculates a difference between the target slice profile and at least one of the first slice profile and the second slice profile.Type: ApplicationFiled: January 23, 2025Publication date: July 31, 2025Inventors: William Grissom, Mark Griswold, Madison M. Albert
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Publication number: 20250167102Abstract: Implementations of a method of making a silicon-on-insulator (SOI) die may include forming a plurality of grooves in a second side of a silicon substrate, depositing an insulative layer directly to the second side of the silicon substrate, the insulative layer filling the plurality of grooves, the silicon substrate comprising a first side opposite the second side, and singulating the silicon substrate through the plurality of grooves into a plurality of SOI die. The insulative layer may be coupled to silicon only through the second side of the silicon substrate.Type: ApplicationFiled: January 17, 2025Publication date: May 22, 2025Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. SEDDON, Mark GRISWOLD
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Publication number: 20250167101Abstract: Implementations of a method of making a silicon-on-insulator (SOI) die may include forming a plurality of grooves in a second side of a silicon substrate, depositing an insulative layer directly to the second side of the silicon substrate, the insulative layer filling the plurality of grooves, the silicon substrate comprising a first side opposite the second side, and singulating the silicon substrate through the plurality of grooves into a plurality of SOI die. The insulative layer may be coupled to silicon only through the second side of the silicon substrate.Type: ApplicationFiled: January 17, 2025Publication date: May 22, 2025Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. SEDDON, Mark GRISWOLD
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Patent number: 12284834Abstract: In an example, a semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of the first conductivity type over the semiconductor substrate. A well region of a second conductivity type is in the semiconductor region. A doped region of the first conductivity type is in the well region. A doped region of the second conductivity type is in the well region. A doped region of the second conductivity type is in the semiconductor substrate at a bottom side. A doped region of the first conductivity type is in the semiconductor substrate at the bottom side. A first conductor is at a top side of the semiconductor region and a second conductor is at the bottom side. In some examples, one or more of doped regions at the bottom side is a patterned doped region.Type: GrantFiled: July 19, 2024Date of Patent: April 22, 2025Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Derrick Johnson, Yupeng Chen, Ralph N. Wall, Mark Griswold
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Publication number: 20250111799Abstract: Systems, methods, and media for simulating interactions with an infant are provided. In some embodiments, a system comprises: a display; and at least one processor, wherein the at least one processor is programmed to: receive input to add a state; receive input setting one or more parameters associated with the state; cause content to be presented based on the parameters via the display; save the parameters; cause a simulation to be created; receive a selection of the state; and cause a simulated infant in the simulation to be presented based on the one or more parameters.Type: ApplicationFiled: January 17, 2023Publication date: April 3, 2025Inventors: Mark Griswold, Henry Eastman, Anastasiya Kurylyuk, James Gasparatos, Erin Henninger, Mary C. Ottolini, Michael A. Ferguson, Misty Melendi, Allison Zanno
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Patent number: 12211784Abstract: Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.Type: GrantFiled: February 29, 2024Date of Patent: January 28, 2025Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Mark Griswold, Michael J. Seddon
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Publication number: 20250007985Abstract: Systems, methods, and media for controlling shared extended reality presentations are provided. In some embodiments, the system comprises: a display; and a processor programmed to: receive an indication that a computing device has joined a presentation; cause a user interface element that represents the computing device to be presented within a graphical user interface (GUI); receive, via the GUI, input indicating that the computing device is to be associated with a group of computing devices; associate the computing device with the group; cause the user interface element that represents the computing device to be presented within a portion of the GUI associated with the group of computing devices; receive, via the GUI, input to cause the group of computing devices to present particular extended reality content; and transmit an instruction to each computing device in the group of computing devices to present the particular extended reality content.Type: ApplicationFiled: November 14, 2022Publication date: January 2, 2025Inventors: Henry Eastman, Robert Gotschall, Jeffrey Mlakar, Mark Griswold, James Gasparatos, Erin Henninger
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Publication number: 20240387510Abstract: In an example, a semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of the first conductivity type over the semiconductor substrate. A well region of a second conductivity type is in the semiconductor region. A doped region of the first conductivity type is in the well region. A doped region of the second conductivity type is in the well region. A doped region of the second conductivity type is in the semiconductor substrate at a bottom side. A doped region of the first conductivity type is in the semiconductor substrate at the bottom side. A first conductor is at a top side of the semiconductor region and a second conductor is at the bottom side. In some examples, one or more of doped regions at the bottom side is a patterned doped region.Type: ApplicationFiled: July 19, 2024Publication date: November 21, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Derrick JOHNSON, Yupeng CHEN, Ralph N. WALL, Mark GRISWOLD
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Patent number: 12087760Abstract: In an example, a semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of the first conductivity type over the semiconductor substrate. A well region of a second conductivity type is in the semiconductor region. A doped region of the first conductivity type is in the well region. A doped region of the second conductivity type is in the well region. A doped region of the second conductivity type is in the semiconductor substrate at a bottom side. A doped region of the first conductivity type is in the semiconductor substrate at the bottom side. A first conductor is at a top side of the semiconductor region and a second conductor is at the bottom side. In some examples, one or more of doped regions at the bottom side is a patterned doped region.Type: GrantFiled: May 6, 2022Date of Patent: September 10, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Derrick Johnson, Yupeng Chen, Ralph N. Wall, Mark Griswold
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Publication number: 20240261057Abstract: Systems, methods, and media for presenting biophysical simulations in an interactive mixed reality environment are provided. In some embodiments, a system comprises: a head mounted display comprising: a transparent display; sensors; and a processor programmed to: receive medical imaging data associated with a subject; receive, from a server, information useable to visualize a simulation of biophysical processes and a subject-specific anatomical model based on the medical imaging data; cause a visualization of the simulation to be presented, via the transparent display, in connection with the medical imaging data and an instrument in a first position; receive, from the server, updated information useable to visualize an updated simulation with the instrument in a second position; and cause a visualization of the updated simulation to be presented with the instrument presented in the second position.Type: ApplicationFiled: June 3, 2022Publication date: August 8, 2024Inventors: Cameron McIntyre, Angela Noecker, Jeffrey Mlakar, Mark Griswold
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Publication number: 20240203864Abstract: Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.Type: ApplicationFiled: February 29, 2024Publication date: June 20, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Mark GRISWOLD, Michael J. SEDDON
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Patent number: 11984471Abstract: In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed into a pattern of a polygon spiral. An embodiment of the pattern of the resistor includes sides and corners. The material of the sides has a low resistivity and the material of the corners has a higher resistivity.Type: GrantFiled: September 20, 2021Date of Patent: May 14, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Arash Elhami Khorasani, Mark Griswold
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Patent number: 11971467Abstract: A method for free-breathing abdominal magnetic resonance fingerprinting (MRF) includes applying a pilot tone (PT) RF signal in an MRI system environment using a PT RF signal source, acquiring MRF data from a region of interest in subject using free-breathing MRF pulse sequence and acquiring PT navigator signals based on the applied PT RF signal. The PT navigator signals are associated with a plurality of respiratory states and are encoded with acquired MRF data. The method further includes generating images for each of the plurality of respiratory states based on MRF data and the PT navigator signals. For each respiratory state, the generated images for the respiratory state are compared to a respiratory state MRF dictionary associated with the respiratory state to determine tissue property of the MRF data associated with the respiratory state. A quantitative parameter map may be generated for the determined tissue properties for each respiratory state.Type: GrantFiled: March 15, 2021Date of Patent: April 30, 2024Assignee: Case Western Reserve UniversityInventors: Sherry Huang, Mark Griswold
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Patent number: 11948880Abstract: Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.Type: GrantFiled: October 4, 2022Date of Patent: April 2, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Mark Griswold, Michael J. Seddon
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Publication number: 20240055503Abstract: In an example, a semiconductor device includes a region of semiconductor material, a first dielectric over the region of semiconductor material, a first gate conductor over a first portion of the first dielectric, and a second gate conductor over a second portion of the first dielectric and laterally spaced apart from the first gate conductor. A first conductor is coupled to the first gate conductor and a second conductor coupled to the second gate conductor and laterally separated from the first conductor by a first spacing. A second dielectric is within the first spacing. The first conductor and the second conductor are laterally capacitively coupled, the first gate conductor is vertically capacitively coupled to the region of semiconductor material, and the second gate conductor is vertically capacitively coupled to the region of semiconductor material.Type: ApplicationFiled: August 10, 2022Publication date: February 15, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Arash ELHAMI KHORASANI, Mark GRISWOLD
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Publication number: 20240047578Abstract: In one embodiment, a transistor has a drift region that is formed to have a plurality of zones having different vertical doping profiles across the zones. At least one of the zones has a vertical doping profile that has a first peak near a top surface of the zone and a second peak near a bottom surface. An embodiment may have a lower doping in a region that is between the two peaks.Type: ApplicationFiled: October 19, 2023Publication date: February 8, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Weize CHEN, Mark GRISWOLD
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Publication number: 20230361107Abstract: In an example, a semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of the first conductivity type over the semiconductor substrate. A well region of a second conductivity type is in the semiconductor region. A doped region of the first conductivity type is in the well region. A doped region of the second conductivity type is in the well region. A doped region of the second conductivity type is in the semiconductor substrate at a bottom side. A doped region of the first conductivity type is in the semiconductor substrate at the bottom side. A first conductor is at a top side of the semiconductor region and a second conductor is at the bottom side. In some examples, one or more of doped regions at the bottom side is a patterned doped region.Type: ApplicationFiled: May 6, 2022Publication date: November 9, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Derrick JOHNSON, Yupeng CHEN, Ralph N. WALL, Mark GRISWOLD
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Patent number: 11810976Abstract: In one embodiment, a transistor has a drift region that is formed to have a plurality of zones having different vertical doping profiles across the zones. At least one of the zones has a vertical doping profile that has a first peak near a top surface of the zone and a second peak near a bottom surface. An embodiment may have a lower doping in a region that is between the two peaks.Type: GrantFiled: February 18, 2021Date of Patent: November 7, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Weize Chen, Mark Griswold
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Publication number: 20230176156Abstract: A method for free-breathing abdominal magnetic resonance fingerprinting (MRF) includes applying a pilot tone (PT) RF signal in an MRI system environment using a PT RF signal source, acquiring MRF data from a region of interest in subject using free-breathing MRF pulse sequence and acquiring PT navigator signals based on the applied PT RF signal. The PT navigator signals are associated with a plurality of respiratory states and are encoded with acquired MRF data. The method further includes generating images for each of the plurality of respiratory states based on MRF data and the PT navigator signals. For each respiratory state, the generated images for the respiratory state are compared to a respiratory state MRF dictionary associated with the respiratory state to determine tissue property of the MRF data associated with the respiratory state. A quantitative parameter map may be generated for the determined tissue properties for each respiratory state.Type: ApplicationFiled: March 15, 2021Publication date: June 8, 2023Inventors: Sherry Huang, Mark Griswold
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Publication number: 20230025410Abstract: Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.Type: ApplicationFiled: October 4, 2022Publication date: January 26, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Mark GRISWOLD, Michael J. SEDDON