Abstract: Optimizations are provided for processing environments. Selected memory objects are tagged with unique identifiers by an operating system of the environment, and those identifiers are used to manage processing within the environment. By detecting by a processing platform of the environment that a memory object has been tagged with a unique identifier, certain tasks may be bypassed and/or memory objects may be reused, even if located at a different location.

Abstract: Memory consistency is provided in an emulated processing environment. A processor architected with a weak memory consistency emulates an architecture having a firm memory consistency. This memory consistency is provided without requiring serialization instructions or special hardware.

Abstract: Instruction execution is facilitated by employing a buffer to handle instructions having special circumstances. When such an instruction is to be executed, a pointer of the instruction is directed to the buffer. The instruction is executed from the buffer and then the pointer is recovered to point to a location other than the buffer.

Abstract: A method, system and program product are provided for establishing one or more decimal floating point (DFP) operand for facilitating testing of a decimal floating point instruction. The method includes obtaining an encoded DFP operand previously generated for testing the decimal floating point instruction, and logically modifying at least one bit of the encoded DFP operand without decoding the encoded DFP operand to obtain an additional encoded DFP operand. In one embodiment, m sequential bits of the encoded DFP operand, n randomly generated bits (wherein n=m), and a logical operation (such as an AND, OR, XOR or SHIFT) are employed in modifying the previously generated, encoded DFP operand.

Abstract: Instruction execution is controlled by a single test that determines whether processing should continue in mainline processing or fall through to a test set. The single test compares a dynamically set variable to an instruction counter. If the test is met, mainline processing continues. Otherwise, processing falls through to a test set.

Abstract: Communication between processors and I/O communications processes is facilitated. During the communication, shared control blocks and input/output queues are updated without using locks. Instead, a lockless capability is provided to update the queues and control blocks, thereby enhancing system performance and minimizing the need for recovery processes.

Abstract: A data structure of readily accessible units of memory is provided. The data structure includes designations of one or more units of memory that while represented in the data structure do not need expensive address translation, other tests or special handling in order to access the units of memory. By employing such a data structure, memory access and system performance are enhanced.

Abstract: Communication between processors and I/O communications processes is facilitated. During the communication, shared control blocks and input/output queues are updated without using locks. Instead, a lockless capability is provided to update the queues and control blocks, thereby enhancing system performance and minimizing the need for recovery processes.

Abstract: Memory consistency is provided in an emulated processing environment. A processor architected with a weak memory consistency emulates an architecture having a firm memory consistency. This memory consistency is provided without requiring serialization instructions or special hardware.

Abstract: A data structure of readily accessible units of memory is provided. The data structure includes designations of one or more units of memory that while represented in the data structure do not need expensive address translation, other tests or special handling in order to access the units of memory. By employing such a data structure, memory access and system performance are enhanced.

Abstract: Instruction execution is facilitated by employing a buffer to handle instructions having special circumstances. When such an instruction is to be executed, a pointer of the instruction is directed to the buffer. The instruction is executed from the buffer and then the pointer is recovered to point to a location other than the buffer.

Abstract: Instruction execution is controlled by a single test that determines whether processing should continue in mainline processing or fall through to a test set. The single test compares a dynamically set variable to an instruction counter. If the test is met, mainline processing continues. Otherwise, processing falls through to a test set.

Abstract: An exemplary embodiment of the invention relates to a system for facilitating coverage feedback testcase generation reproducibility. The system comprises a domain definition input file for defining a coverage domain element and an internal coverage domain data store in communication with the domain definition input file. The internal coverage domain data store stores domain definitions collected from the domain definition input file as well as updates made to the coverage domain element. The system also includes a test case generator in communication with the internal coverage domain data store. The test case generator generates testcases. The system also includes a pseudo-random generated seed assigned to a successfully generated testcase. The successfully generated testcase is replicated without generating each prior testcase utilizing the pseudo-random generated seed. The replication includes an initial coverage state for the successfully generated testcase.

Abstract: A method, system and program product are provided for establishing one or more decimal floating point (DFP) operand for facilitating testing of a decimal floating point instruction. The method includes obtaining an encoded DFP operand previously generated for testing the decimal floating point instruction, and logically modifying at least one bit of the encoded DFP operand without decoding the encoded DFP operand to obtain an additional encoded DFP operand. In one embodiment, m sequential bits of the encoded DFP operand, n randomly generated bits (wherein n=m), and a logical operation (such as an AND, OR, XOR or SHIFT) are employed in modifying the previously generated, encoded DFP operand.

Abstract: The invention relates to a system and method for facilitating programmable coverage domains for test case generation, feedback, and measurement. The system comprises a domain definition input file; user-defined coverage domain data entered into the domain definition input file; and a parser operable for translating the user-defined coverage domain data into machine-readable computer program code. The system further includes an internal coverage domain comprising: a union of enabled coverage domains extracted from the user-defined coverage domain data; a session component comprising a session update count for each domain element; and a history component comprising a history update count for each domain element. The system further comprises a testcase generator including an internal coverage feedback and measurement system.

Abstract: A method for specifying a set of instructions selectable for generation by an instruction generator is disclosed. A class name representative of a class of instructions is identified and concatenated with a unique identifier label, thereby defining a unique singleton meta-mnemonic representative of a set of instructions. The class of instructions and the set of instructions are subsets of the instruction set of the processor. The resulting singleton meta-mnemonic specifies the set of instructions available for selection and generation by the instruction generator.

Abstract: A method for a method for testing the validity of shared data in a multiprocessing system is disclosed. The method comprises receiving at a first central processing unit a list of fetch and store instructions associated with blocks in a shared memory location. The list includes a data value, a central processing unit identifier and a relative order associated with the instructions. In addition, one of the data values associated with one of the instructions was stored by a memory-to-memory, memory-to-register or register-to-memory operation. Further, one of the central processing unit identifiers associated with one of the instructions is an identifier corresponding to one of a plurality of central processing units that have access to the shared memory location including the first central processing unit. A fetch operation is performed at a block in the shared memory location from the first central processing unit.

Abstract: An exemplary embodiment of the invention relates to a system for facilitating coverage feedback testcase generation reproducibility. The system comprises a domain definition input file for defining a coverage domain element and an internal coverage domain data store in communication with the domain definition input file. The internal coverage domain data store stores domain definitions collected from the domain definition input file as well as updates made to the coverage domain element. The system also incudes a test case generator in communication with the internal coverage domain data store. The test case generator generates testcases. The system also includes a pseudo-random generated seed assigned to a successfully generated testcase. The successfully generated testcase is replicated without generating each prior testcase utilizing the pseudo-random generated seed. The replication includes an initial coverage state for the successfully generated testcase.

Abstract: A method for a method for testing the validity of shared data in a multiprocessing system is disclosed. The method comprises receiving at a first central processing unit a list of fetch and store instructions associated with blocks in a shared memory location. The list includes a data value, a central processing unit identifier and a relative order associated with the instructions. In addition, one of the data values associated with one of the instructions was stored by a memory-to-memory, memory-to-register or register-to-memory operation. Further, one of the central processing unit identifiers associated with one of the instructions is an identifier corresponding to one of a plurality of central processing units that have access to the shared memory location including the first central processing unit. A fetch operation is performed at a block in the shared memory location from the first central processing unit.

Abstract: An exemplary embodiment of the invention relates to a system and method for facilitating coverage feedback testcase generation reproducibility. The system comprises: a testcase generator comprising an instruction generator and an instruction simulator; an internal coverage domain accessible to the testcase generator, a regeneration file storing updated testcase data; and a temporary holding structure. The internal coverage domain comprises: coverage domain elements; a session component; and a prior cumulative history component. Upon generating a testcase by the testcase generator, a regeneration file is constructed utilizing testcase data updates acquired during execution of the testcase. The updates are provided by the temporary holding structure. The invention also comprises a method and storage medium.