Abstract: A digital motion video processing circuit can capture, playback and manipulate digital motion video information using the system memory of a computer as a data buffer for holding compressed video data from the circuit. The system memory may be accessed by the circuit over a standard bus. A controller in the circuit directs data flow between an input/output port which transfer a stream of pixel data and to the standard bus. The controller directs data to and from either the standard bus or the input/output port through processing circuitry for compression, decompression, scaling and buffering. The standard bus may be a peripheral component interconnect (PCI) bus. The motion video processing circuit has a data path including pixel data and timing data indicative of a size of an image defined by the pixel data. The timing data is used and/or generated by each component which processes the pixel data, thereby enabling each component to process the pixel data without prior knowledge of the image format.

Abstract: A digital motion video processing circuit can capture, playback and manipulate digital motion video information using the system memory of a computer as a data buffer for holding compressed video data from the circuit. The system memory may be accessed by the circuit over a standard bus. A controller in the circuit directs data flow between an input/output port which transfer a stream of pixel data and to the standard bus. The controller directs data to and from either the standard bus or the input/output port through processing circuitry for compression, decompression, scaling and buffering. The standard bus may be a peripheral component interconnect (PCI) bus. The motion video processing circuit has a data path including pixel data and timing data indicative of a size of an image defined by the pixel data. The timing data is used and/or generated by each component which processes the pixel data, thereby enabling each component to process the pixel data without prior knowledge of the image format.

Abstract: A data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and a main store bus connected to the controller. At least one processor of a first type is connected to the main store bus, this being an auxiliary processor for performing input-output and other operations. At least one processor of a second type also is connected to the main store bus, this being an execution processor for fetching, decoding and executing instructions. All or some of either or both of the auxiliary processors and execution processors may be different. A supervisory processor for initiating configuring and monitoring the system is connected to the main store bus. A communication bus is connected to the processors of the first and second types and to the supervisory processor. A diagnostic bus connects the supervisory processor to each of the processors of the first and second types.

Abstract: A data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and a main store bus connected to the controller. At least one processor of a first type is connected to the main store bus, this being an auxiliary processor for performing input-output and other operations. At least one processor of a second type also is connected to the main store bus, this being an execution processor for fetching, decoding and executing instructions. All or some of either or both of the auxiliary processors and execution processors may be different. A supervisory processor for initiating configuring and monitoring the system is connected to the main store bus. A communication bus is connected to the processors of the first and second types and to the supervisory processor. A diagnostic bus connects the supervisory processor to each of the processors of the first and second types.

Abstract: A data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and a main store bus connected to the controller. At least one processor of a first type is connected to the main store bus, this being an auxiliary processor for performing input-output and other operations. At least one processor of a second type also is connected to the main store bus, this being an execution processor for fetching, decoding and executing instructions. All or some of either or both of the auxiliary processors and execution processors may be different. A supervisory processor for initiating configuring and monitoring the system is connected to the main store bus. A communication bus is connected to the processors of the first and second types and to the supervisory processor. A diagnostic bus connects the supervisory processor to each of the processors of the first and second types.

Abstract: An adapter for transferring the electrical connections of a circuit card of an electrical system from a fixed connector in a congested chassis area on one side of a master interconnect board to a convenient access area on the opposite side of the master board. The adapter comprises a first electrical connector element for making electrical connection to the system at a location on the opposite side of the master board in correspondence with the fixed connector, a second electrical connector element for making electrical connection to the circuit card, and an element for joining the first and second electrical connector elements mechanically and electrically adjacent the opposite side of the master board.