Abstract: A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.

Abstract: A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

Abstract: A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.

Abstract: A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

Abstract: A CAM may include a plurality of CAM cells. Each CAM cell is configured to generate an output indicating if a corresponding input bit and the bit stored in that CAM cell match. A circuit is configured to logically AND the outputs to generate a hit output. A first compare line generator circuit is configured to generate a first pulse responsive to a clock signal and a data signal and a second compare line generator circuit is configured to generate a second pulse responsive to the clock signal and the complement of the data signal. A CAM may include a circuit configured to generate a pulse indicating a hit in an entry of the CAM and a latch circuit configured to capture the pulse responsive to the first clock signal and configured to clear responsive to the second clock signal. A first CAM may store a value in each entry and may further store a compare result.

Abstract: A CAM may include a plurality of CAM cells. Each CAM cell is configured to generate an output indicating if a corresponding input bit and the bit stored in that CAM cell match. A circuit is configured to logically AND the outputs to generate a hit output. A first compare line generator circuit is configured to generate a first pulse responsive to a clock signal and a data signal and a second compare line generator circuit is configured to generate a second pulse responsive to the clock signal and the complement of the data signal. A CAM may include a circuit configured to generate a pulse indicating a hit in an entry of the CAM and a latch circuit configured to capture the pulse responsive to the first clock signal and configured to clear responsive to the second clock signal. A first CAM may store a value in each entry and may further store a compare result.

Abstract: A CAM may include a plurality of CAM cells. Each CAM cell is configured to generate an output indicating if a corresponding input bit and the bit stored in that CAM cell match. A circuit is configured to logically AND the outputs to generate a hit output. A first compare line generator circuit is configured to generate a first pulse responsive to a clock signal and a data signal and a second compare line generator circuit is configured to generate a second pulse responsive to the clock signal and the complement of the data signal. A CAM may include a circuit configured to generate a pulse indicating a hit in an entry of the CAM and a latch circuit configured to capture the pulse responsive to the first clock signal and configured to clear responsive to the second clock signal. A first CAM may store a value in each entry and may further store a compare result.

Abstract: A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.

Abstract: A CAM may include a plurality of CAM cells. Each CAM cell is configured to generate an output indicating if a corresponding input bit and the bit stored in that CAM cell match. A circuit is configured to logically AND the outputs to generate a hit output. A first compare line generator circuit is configured to generate a first pulse responsive to a clock signal and a data signal and a second compare line generator circuit is configured to generate a second pulse responsive to the clock signal and the complement of the data signal. A CAM may include a circuit configured to generate a pulse indicating a hit in an entry of the CAM and a latch circuit configured to capture the pulse responsive to the first clock signal and configured to clear responsive to the second clock signal. A first CAM may store a value in each entry and may further store a compare result.

Abstract: A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.