Patents by Inventor Mark Hamlyn
Mark Hamlyn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105721Abstract: Devices with increased susceptibility to ionizing radiation feature multiple parasitic transistors having leakage currents that increase with total ionizing dose (TID) due to negative threshold shifts from radiation-induced charge buildup in the field oxide. Leakage currents of parasitic edge transistors associated with active region sidewalls under a gate are enhanced using branching gate patterns that increase the number of these sidewalls. Other variations combine parasitic edge transistors with parasitic field transistors formed under the field oxide between active regions, or between n-wells and active regions. Arrays of such devices connected in parallel further multiply leakage currents, while novel compact designs increase the density and hence the sensitivity to TID for a given circuit area.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Applicant: Apogee Semiconductor, Inc.Inventors: Emily Ann Donnelly, Mark Hamlyn, Kyle Schulmeyer, Gregory A. Magel
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Patent number: 11862724Abstract: Compact radiation-hardened NMOS transistors permitting close spacing for high circuit density can be fabricated using modern commercial foundry processes incorporating lightly-doped drain (LDD) and silicidation techniques. Radiation-induced leakage currents in parasitic field oxide transistors are reduced by spacing diffusions away from field oxide edges under the gate, forming gap regions from which n-type dopants and silicide formation are excluded using blocking patterns in the layout. P-type implants along these field oxide edges further increase radiation tolerance. Dimensions can be tailored to permit tradeoffs between radiation tolerance, breakdown voltage, and circuit density. Compact layouts for series-connected NMOS transistors are provided and applied to high-density rad-hard circuits. Methods for fabricating devices having these features are also provided, requiring minimal adaptation of standard processes.Type: GrantFiled: September 1, 2023Date of Patent: January 2, 2024Assignee: Apogee Semiconductor, Inc.Inventor: Mark Hamlyn
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Patent number: 11847084Abstract: CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.Type: GrantFiled: June 2, 2023Date of Patent: December 19, 2023Assignee: Apogee Semiconductor, Inc.Inventors: Mark Hamlyn, David A. Grant
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Patent number: 11848673Abstract: An integrated circuit for use in high-reliability electronic systems contains one or more digital majority voters with corresponding disagreement detectors connected to the same input signals producing a majority value output and an error signal that is active when not all input signals agree. Internal error signals from multiple majority voter/disagreement detectors as well as external error inputs may be combined using disjunctive error logic to produce an “error detected” output indication. Cold-sparing and hot-plugging are supported by providing cold-sparable electrostatic discharge protection circuits and power-on reset circuitry controlling cold-sparable output stages. Internal modular redundancy provides immunity to single-event transients as well as enhanced reliability.Type: GrantFiled: August 16, 2023Date of Patent: December 19, 2023Assignee: Apogee Semiconductor, Inc.Inventors: David A. Grant, Mark Hamlyn
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Patent number: 11791831Abstract: Systems and methods for fault-tolerant threshold circuits used in converting an analog input to a single-bit digital output employ N-modular redundancy of either inverting or non-inverting threshold circuits whose inputs are connected to a single input, and apply majority voting of their outputs to provide correction of transient or permanent faults in up to floor[(N?1)/2] of the individual threshold circuits. Using summation to perform analog majority voting averages the N threshold circuit outputs and provides resilience to single-event transients, but may exhibit an output characteristic having intermediate voltage levels. A digital majority voter having N inputs connected to the outputs of N threshold circuits restores well-defined logic levels and clean hysteresis for Schmitt trigger threshold circuits. A single point of failure at the digital majority voter may be eliminated using an analog majority voter to sum the outputs of three or more redundant digital majority voters.Type: GrantFiled: May 19, 2023Date of Patent: October 17, 2023Assignee: Apogee Semiconductor, Inc.Inventors: David A. Grant, Mark Hamlyn
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Patent number: 11784250Abstract: Compact radiation-hardened NMOS transistors permitting close spacing for high circuit density can be fabricated using modern commercial foundry processes incorporating lightly-doped drain (LDD) and silicidation techniques. Radiation-induced leakage currents in parasitic field oxide transistors are reduced by spacing diffusions away from field oxide edges under the gate, forming gap regions from which n-type dopants and silicide formation are excluded using blocking patterns in the layout. P-type implants along these field oxide edges further increase radiation tolerance. Dimensions can be tailored to permit tradeoffs between radiation tolerance, breakdown voltage, and circuit density. Compact layouts for series-connected NMOS transistors are provided and applied to high-density rad-hard circuits. Methods for fabricating devices having these features are also provided, requiring minimal adaptation of standard processes.Type: GrantFiled: February 2, 2023Date of Patent: October 10, 2023Assignee: Apogee Semiconductor, Inc.Inventor: Mark Hamlyn
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Publication number: 20230305984Abstract: CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.Type: ApplicationFiled: June 2, 2023Publication date: September 28, 2023Applicant: Apogee Semiconductor, Inc.Inventors: Mark Hamlyn, David A. Grant
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Patent number: 11726943Abstract: CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.Type: GrantFiled: March 6, 2021Date of Patent: August 15, 2023Assignee: Apogee Semiconductor, Inc.Inventors: Mark Hamlyn, David A. Grant
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Publication number: 20210279197Abstract: CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.Type: ApplicationFiled: March 6, 2021Publication date: September 9, 2021Applicant: TallannQuest LLC DBA Apogee SemiconductorInventors: Mark Hamlyn, David A. Grant
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Patent number: 9018923Abstract: Apparatus and methods operate to disable a dynamically biased apparatus and a dynamic bias current source providing dynamic bias current to the apparatus at the beginning of a static bias startup period shortly after power-on. The dynamically biased apparatus is then gradually enabled in a static bias mode of operation during the static bias startup period. Following the end of the static bias startup period, operation of the dynamically biased apparatus in a dynamic transconductance mode is gradually enabled during a dynamic bias startup period. Such startup sequence operates to prevent damaging in-rush currents in a system employing the dynamically biased apparatus in a feedback control loop.Type: GrantFiled: December 5, 2011Date of Patent: April 28, 2015Assignee: Texas Instruments IncorporatedInventors: Charles Parkhurst, Mark Hamlyn
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Patent number: 8896323Abstract: Systems and methods for radiation-tolerant overcurrent detection are disclosed. In some embodiments, an integrated circuit may include a plurality of overcurrent detectors, each of the plurality of overcurrent detectors configured to detect a candidate overcurrent event. The integrated circuit may also include a voting circuit coupled to the overcurrent detectors, the voting circuit configured to indicate an overcurrent in response to receiving a selected number of candidate overcurrent events from the overcurrent detectors. At least one of the overcurrent detectors may be subject to detecting the candidate overcurrent in error, at least in part, due to exposure to ionizing radiation.Type: GrantFiled: October 21, 2011Date of Patent: November 25, 2014Assignee: Texas Instruments IncorporatedInventors: Charles Parkhurst, Mark Hamlyn
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Publication number: 20130141059Abstract: Apparatus and methods operate to disable a dynamically biased apparatus and a dynamic bias current source providing dynamic bias current to the apparatus at the beginning of a static bias startup period shortly after power-on. The dynamically biased apparatus is then gradually enabled in a static bias mode of operation during the static bias startup period. Following the end of the static bias startup period, operation of the dynamically biased apparatus in a dynamic transconductance mode is gradually enabled during a dynamic bias startup period. Such startup sequence operates to prevent damaging in-rush currents in a system employing the dynamically biased apparatus in a feedback control loop.Type: ApplicationFiled: December 5, 2011Publication date: June 6, 2013Inventors: Charles Parkhurst, Mark Hamlyn
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Patent number: 8436682Abstract: Apparatus and methods disclosed herein operate to receive a differential input signal at a first-stage pair of transconductance devices. The differential signal is amplified by a second-order factor at a positive-side or a negative-side first-stage transconductance device, depending upon the polarity of the differential input signal, to create a second-order signal at the output of the appropriate first-stage device. The second-order output signal is then amplified by another second-order factor at a corresponding second-stage transconductance device. A resulting fourth-order signal is made available at an output node as a quartic-response current source. The quartic-response current source may be utilized as a dynamic bias source in conjunction with a linear amplifier to provide a high slew rate amplifier.Type: GrantFiled: October 21, 2011Date of Patent: May 7, 2013Assignee: Texas Instruments IncorporatedInventors: Charles Parkhurst, Mark Hamlyn
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Publication number: 20130099863Abstract: Apparatus and methods disclosed herein operate to receive a differential input signal at a first-stage pair of transconductance devices. The differential signal is amplified by a second-order factor at a positive-side or a negative-side first-stage transconductance device, depending upon the polarity of the differential input signal, to create a second-order signal at the output of the appropriate first-stage device. The second-order output signal is then amplified by another second-order factor at a corresponding second-stage transconductance device. A resulting fourth-order signal is made available at an output node as a quartic-response current source. The quartic-response current source may be utilized as a dynamic bias source in conjunction with a linear amplifier to provide a high slew rate amplifier.Type: ApplicationFiled: October 21, 2011Publication date: April 25, 2013Inventors: Charles Parkhurst, Mark Hamlyn
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Publication number: 20130099796Abstract: Systems and methods for radiation-tolerant overcurrent detection are disclosed. In some embodiments, an integrated circuit may include a plurality of overcurrent detectors, each of the plurality of overcurrent detectors configured to detect a candidate overcurrent event. The integrated circuit may also include a voting circuit coupled to the overcurrent detectors, the voting circuit configured to indicate an overcurrent in response to receiving a selected number of candidate overcurrent events from the overcurrent detectors. At least one of the overcurrent detectors may be subject to detecting the candidate overcurrent in error, at least in part, due to exposure to ionizing radiation.Type: ApplicationFiled: October 21, 2011Publication date: April 25, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Charles Parkhurst, Mark Hamlyn
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Patent number: 8390327Abstract: A system and method for radiation-tolerant level shifting are disclosed. In some embodiments, an integrated circuit may include a plurality of level shifters, where each of the plurality of level shifters configured receive a same logic level in a first voltage domain and to output candidate logic levels in a second voltage domain, and where at least one of the candidate logic levels subject to being different from another one of the candidate logic levels. The integrated circuit may also include a voting circuit coupled to the plurality of level shifters, where the voting circuit is configured to evaluate the candidate logic levels and output a selected logic level based, at least in part, upon the evaluation.Type: GrantFiled: August 19, 2011Date of Patent: March 5, 2013Assignee: Texas Instruments IncorporatedInventors: Charles Parkhurst, Mark Hamlyn
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Publication number: 20130043903Abstract: A system and method for radiation-tolerant level shifting are disclosed. In some embodiments, an integrated circuit may include a plurality of level shifters, where each of the plurality of level shifters configured receive a same logic level in a first voltage domain and to output candidate logic levels in a second voltage domain, and where at least one of the candidate logic levels subject to being different from another one of the candidate logic levels. The integrated circuit may also include a voting circuit coupled to the plurality of level shifters, where the voting circuit is configured to evaluate the candidate logic levels and output a selected logic level based, at least in part, upon the evaluation.Type: ApplicationFiled: August 19, 2011Publication date: February 21, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Charles Parkhurst, Mark Hamlyn