Abstract: Apparatus might include an array of memory cells and a controller to perform access operations on the array of memory cells. The controller might be configured to establish a negative potential in a body of a memory cell of the array of memory cells, and initiate a sensing operation on the memory cell while the body of the memory cell has the negative potential. Apparatus might further include an array of memory cells, a timer, and a controller to perform access operations on the array of memory cells. The controller might be configured to advance the timer, and establish a negative potential in a body of a memory cell of the array of memory cells in response to a value of the timer having a desired value.

Abstract: Devices and techniques to recover data from a memory device are disclosed, including recovering data corresponding to a detected error in data stored on a memory array corresponding to a memory operation using one of a set of read offset values and loading the one of the set of read offset values used to recover data corresponding to the detected error in a temporary storage of the memory array as a custom read offset value for a subsequent memory operation. The temporary storage of the memory array can include a scratch space of the memory array separate from read retry offset registers of the memory device.

Abstract: Devices and techniques to recover data from a memory device using a custom Read Retry feature are disclosed herein. A memory device can receive a first read request, read data from the memory array corresponding to the read request, and determine if the read data corresponding to the first read request includes a detectable error. In response to a detected error in the received data corresponding to the first read request, the memory device can recover data corresponding to the first read request using one of a set of read retry features, and load the one of the set of read retry features used to recover data corresponding to the first read request as a custom read retry feature in the memory device for a second read request subsequent to the first read request.

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

Abstract: Apparatus might include an array of memory cells and a controller to perform access operations on the array of memory cells. The controller might be configured to establish a negative potential in a body of a memory cell of the array of memory cells, and initiate a sensing operation on the memory cell while the body of the memory cell has the negative potential. Apparatus might further include an array of memory cells, a timer, and a controller to perform access operations on the array of memory cells. The controller might be configured to advance the timer, and establish a negative potential in a body of a memory cell of the array of memory cells in response to a value of the timer having a desired value.

Abstract: Apparatus configured to establish a negative potential in a body of a memory cell during an access operation of another memory cell, and methods of operating such an apparatus, as well as apparatus configured to establish a negative potential in a body of a memory cell in response to a timer, or before a sensing operation of the memory cell.

Abstract: Devices and techniques to recover data from a memory device using a custom Read Retry feature are disclosed herein. A memory device can receive a first read request, read data from the memory array corresponding to the read request, and determine if the read data corresponding to the first read request includes a detectable error. In response to a detected error in the received data corresponding to the first read request, the memory device can recover data corresponding to the first read request using one of a set of read retry features, and load the one of the set of read retry features used to recover data corresponding to the first read request as a custom read retry feature in the memory device for a second read request subsequent to the first read request.

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

Abstract: Apparatus configured to establish a negative potential in a body of a memory cell during an access operation of another memory cell, and methods of operating such an apparatus, as well as apparatus configured to establish a negative potential in a body of a memory cell in response to a timer, or before a sensing operation of the memory cell.

Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell in response to a timer, or during an access operation of another memory cell.

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell in response to a timer, or during an access operation of another memory cell.

Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation on the memory cell, in response to a timer, or during an access operation of another memory cell.

Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation on the memory cell, in response to a timer, or during an access operation of another memory cell.

Abstract: The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells.

Abstract: The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells.

Abstract: The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells, wherein the array includes a first memory cell and a second memory cell, wherein the first and second memory cells are each programmable to one of a number of program states, and wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states. A number of embodiments also include a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and determine soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program state of the first memory cell and the soft data associated with the program state of the second memory cell.

Abstract: Methods of loading trim address and trim data pairs to a trim register array, and apparatus configured to perform such methods. The methods maintain a correspondence between the trim address and the trim data of each trim address and trim data pair in the trim register array. The trim address of a particular trim address and trim data pair corresponds to a storage location of a trim settings array containing trim settings used in performing operations on an array of memory cells. The trim data of the particular trim address and trim data pair corresponds to data to modify a value of the storage location of the trim settings array corresponding to the trim address of the particular trim address and trim data pair.