Abstract: A computing system is configured to securely boot different operating systems. The computing system includes one or more processors, a first memory device storing a first firmware element for booting a first operating system, a second memory device storing a second firmware element for booting a second operating system, a first security module configured to provide authentication for booting the first operating system, and a second security module configured to provide authentication for booting the second operating system. The computing system is configured such that, when the first security module is connected to the one or more processors, either the first operating system or the second operating system is selected for booting based on a selection signal, and when the first security module is not connected to the one or more processors, the second operating system is selected for booting.

Abstract: A computing system is configured to securely boot different operating systems. The computing system includes one or more processors, a first memory device storing a first firmware element for booting a first operating system, a second memory device storing a second firmware element for booting a second operating system, a first security module configured to provide authentication for booting the first operating system, and a second security module configured to provide authentication for booting the second operating system. The computing system is configured such that, when the first security module is connected to the one or more processors, either the first operating system or the second operating system is selected for booting based on a selection signal, and when the first security module is not connected to the one or more processors, the second operating system is selected for booting.

Abstract: An apparatus may include a housing, an electronic display region, and a controller. The electronic display region may be coupled to the housing, and may have a rectangular shape with a length and a width, the length being approximately a square root of two (?2) times longer than the width. In response to an indication that the housing and the display region have been rotated from the portrait mode to a landscape mode, the controller may be configured to display a first image and a second image, the first image having an aspect ratio defined by a second length of the first image divided by a second width of the first image, wherein the second length is different from the first length, the second width is different from the first width, the second aspect ratio is substantially equal to the first aspect ratio, and the first image being rotated by ninety degrees (90°) from the first orientation with respect to the axis.

Abstract: An apparatus may include a housing, an electronic display region, and a controller. The electronic display region may be coupled to the housing, and may have a rectangular shape with a length and a width, the length being approximately a square root of two (?2) times longer than the width. In response to an indication that the housing and the display region have been rotated from the portrait mode to a landscape mode, the controller may be configured to display a first image and a second image, the first image having an aspect ratio defined by a second length of the first image divided by a second width of the first image, wherein the second length is different from the first length, the second width is different from the first width, the second aspect ratio is substantially equal to the first aspect ratio, and the first image being rotated by ninety degrees (90°) from the first orientation with respect to the axis.

Abstract: An apparatus conveniently provides a user with access to applications and data that the user accesses on other devices in a secure and authenticated manner. The apparatus detects the presence of a second device, such as a mobile phone. The apparatus authenticates a user based at least on identifying information provided by the second device. The apparatus locates one or more applications based on resource access information provided by the second device. While the second device remains present, upon authenticating the user, and further upon successfully locating the one or more applications, the apparatus provides the user with access to the one or more applications. User data for the one or more applications is made available from the second device and/or a server. The data is synchronized across all sources. The data is encrypted at the apparatus, and rendered unreadable when the second device is no longer present.

Abstract: An apparatus conveniently provides a user with access to applications and data that the user accesses on other devices in a secure and authenticated manner. The apparatus detects the presence of a second device, such as a mobile phone. The apparatus authenticates a user based at least on identifying information provided by the second device. The apparatus locates one or more applications based on resource access information provided by a server based on the identifying information. While the second device remains present, upon authenticating the user, and further upon successfully locating the application(s), the apparatus provides the user with access to the one or more applications. User data for the one or more applications is made available from the second device and/or a server. The data is synchronized across all sources. The data is encrypted at the apparatus, and rendered unreadable when the second device is no longer present.

Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Abstract: In one embodiment, a system comprises a communication medium; a first controller coupled to the communication medium; and a second controller coupled to the communication medium. The first controller is configured to interrupt transmission of a packet on the communication medium to the second controller subsequent to transmission of a first portion of the packet. The first controller is configured to transmit at least one control symbol on the communication medium in response to interrupting transmission of the packet, and wherein the first controller is configured to continue transmission of the packet with a second portion of the packet. The controller(s) may include, in some embodiments, a media access controller and a physical coding sublayer.

Abstract: In one embodiment, a controller is configured to receive a flow control packet from a link partner on a communication medium. The flow control packet includes a channel indication that indicates one or more channels. The controller is configured to inhibit transmission of packets from at least one channel specified by the channel indication and to permit transmission of packets from channels not specified in the channel indication. The controller may also be configured to transmit the flow control packet in response to detecting a need to flow control one or more channels from the link partner.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.