Abstract: Systems, methods, and media for managing a shared memory cache in a computing system. The management of the shared memory cache can include, for example, determining cache statistics by probabilistically sampling the memory cache: estimating contention of the memory cache based on capturing theft-based contention; and re-partitioning the memory cache based on the cache statistics and the estimated contention. The cache statistics can include thefts and interferences associated with a plurality of cores of the computing system.

Abstract: A method of managing a shared memory cache in a computing memory system. The method includes determining cache statistics by probabilistically sampling the memory cache. Additionally, the method includes estimating contention of the memory cache based on capturing theft-based contention. The method further includes re-partitioning the memory cache based on the cache statistics and the estimated contention.

Abstract: Systems and methods for generating fixed function shared accelerators (FFSAs) implement and/or comprise operations of receiving source code, the source code indicating a plurality of workloads to be performed by an electronic circuit; generating a plurality of abstract syntax trees (ASTs) based on the source code, wherein respective ones of the plurality of ASTs include a plurality of nodes corresponding to function instructions; generating a plurality of fingerprinting vectors corresponding to the plurality of ASTs, wherein respective ones of the plurality of fingerprinting vectors encode at least one of a number of nodes, a number of edges, a density, a computation intensity, an operands percentage, a control, or a data dependency; and providing the plurality of fingerprinting vectors to a machine learning (ML) model, wherein the ML model is configured to predict similarities between different ones of the plurality of workloads and to output at least one candidate FFSA.

Abstract: In some embodiments, the present disclosure provides systems and methods for detecting malware, including receiving thermal images of an integrated circuit, and generating a power density profile using at least one of the thermal images. The present disclosure further includes comparing the power density profile to an expected power density profile of the integrated circuit, and determining, based on the comparison, if the integrated circuit is in an abnormal operating state.

Abstract: In some embodiments, the present disclosure provides systems and methods for detecting malware, including receiving thermal images of an integrated circuit, and generating a power density profile using at least one of the thermal images. The present disclosure further includes comparing the power density profile to an expected power density profile of the integrated circuit, and determining, based on the comparison, if the integrated circuit is in an abnormal operating state.

Abstract: A system for sensor network applications comprising a microcontroller for handling irregular events, at least one hardware accelerator for handling regular events, an event processor for interrupt handling and power management in the system, and a system bus. The microcontroller, hardware accelerator, and event processor each are connected to the system bus. The event processor gates power to the microcontroller to provide power to the microcontroller only for processing related to irregular events requiring processing by the microcontroller. The event processor further may gate power to the hardware accelerator. The system may further include a message processor and a plurality of sensors.