Abstract: A sampling based DBR framework which leverages a separate core for program analysis. The framework includes a hardware performance monitor, a DBR service that executes as a separate process and a lightweight DBR agent that executes within a client process. The DBR service aggregates samples from the hardware performance monitor, performs region selection by deducing the program structure around hot samples, performs transformations on the selected regions (e.g. optimization), and generates replacement code. The DBR agent then patches the client process to use the replacement code.

Abstract: A sampling based DBR framework which leverages a separate core for program analysis. The framework includes a hardware performance monitor, a DBR service that executes as a separate process and a lightweight DBR agent that executes within a client process. The DBR service aggregates samples from the hardware performance monitor, performs region selection by deducing the program structure around hot samples, performs transformations on the selected regions (e.g. optimization), and generates replacement code. The DBR agent then patches the client process to use the replacement code.

Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.

Abstract: A computer system embodies a first hardware (X) architecture for providing an X domain for an X code. The computer system includes a system for simulating a second hardware (Y) architecture providing a Y domain for Y code and for executing the Y code, and a debugger operable in the Y domain for debugging the X and Y codes. The simulating system includes a sub-system for providing support services for the debugger to enable it to debug the Y code, including modification of Y machine state and setting of breakpoints. The computer system also includes a sub-system for generating a call for cross-domain memory data access under predetermined conditions, such as direct memory access failures.

Abstract: A system is provided for executing and debugging multiple codes in a multi-architecture environment that includes a real X architecture (domain) and a simulated (Y) architecture (domain). The multiple code executing and debugging system comprises an X computer system having a memory with stored X and Y code and having the X architecture embodied therein.A detector is provided to detect calls from executing code in either domain for cross-domain services including execution of cross-domain routines. A jacketing system jackets cross-domain routine calls to interface the calling conventions of the calling and the called routines.