Patents by Inventor Mark Hiebert
Mark Hiebert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10284207Abstract: Methods and systems are provided for adaptively configuring voltage-controlled oscillator (VCO) arrays, such as to reduce mismatches among the VCOs. A plurality of voltage-controlled oscillators (VCOs), connected in parallel to a common control input, and with each VCO outputting an oscillating signal based on the common control input and an adjustment input, may be configured to reduce mismatches among the VCOs. The plurality of VCO may be configured by adjusting at least one operational parameter applicable to interconnection paths connecting outputs of the plurality of VCOs; measuring a mismatch between signals at the outputs of the plurality of VCOs with respect to a first signal parameter; and adjusting a first operational parameter applicable to one or more of the plurality of VCOs to reduce mismatch between signals at the outputs of the plurality of VCOs with respect to a first signal parameter.Type: GrantFiled: November 14, 2017Date of Patent: May 7, 2019Assignee: MAXLINEAR ASIA SINGAPORE PTE LTD.Inventors: Mark Hiebert, Srinivasa Rao Madala, Hormoz Djahanshahi
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Patent number: 10270583Abstract: A transmit (TX) signal path circuit in a multiple-input, multiple-output (MIMO) transceiver responsive to a digital front end (DFE) for generating receive (RX) path phase alignment signals is disclosed. A digital up-conversion block uses a first numerically-controlled oscillator (NCO) for generating digital intermediate frequency (IF) signals for ordinary TX signal generation, and a different, second NCO for generating digital IF signals for RX phase alignment signal generation. An RF up-conversion block uses a TX local oscillator (LO) for generating analog RF signals for ordinary TX signal generation, and a different feedback (FB) LO for generating analog RF signals for RX phase alignment signal generation. Thus, phase alignment of the circuitry used for ordinary TX signal generation is left undisturbed by RX phase alignment signal generation.Type: GrantFiled: April 27, 2018Date of Patent: April 23, 2019Assignee: Maxlinear Asia Singapore PTE LTDInventors: Mark Hiebert, Jay Chen
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Publication number: 20180248679Abstract: A transmit (TX) signal path circuit in a multiple-input, multiple-output (MIMO) transceiver responsive to a digital front end (DFE) for generating receive (RX) path phase alignment signals is disclosed. A digital up-conversion block uses a first numerically-controlled oscillator (NCO) for generating digital intermediate frequency (IF) signals for ordinary TX signal generation, and a different, second NCO for generating digital IF signals for RX phase alignment signal generation. An RF up-conversion block uses a TX local oscillator (LO) for generating analog RF signals for ordinary TX signal generation, and a different feedback (FB) LO for generating analog RF signals for RX phase alignment signal generation. Thus, phase alignment of the circuitry used for ordinary TX signal generation is left undisturbed by RX phase alignment signal generation.Type: ApplicationFiled: April 27, 2018Publication date: August 30, 2018Inventors: Mark Hiebert, Jay Chen
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Patent number: 9979534Abstract: A transmit (TX) signal path circuit in a multiple-input, multiple-output (MIMO) transceiver responsive to a digital front end (DFE) for generating receive (RX) path phase alignment signals is disclosed. A digital up-conversion block uses a first numerically-controlled oscillator (NCO) for generating digital intermediate frequency (IF) signals for ordinary TX signal generation, and a different, second NCO for generating digital IF signals for RX phase alignment signal generation. An RF up-conversion block uses a TX local oscillator (LO) for generating analog RF signals for ordinary TX signal generation, and a different feedback (FB) LO for generating analog RF signals for RX phase alignment signal generation. Thus, phase alignment of the circuitry used for ordinary TX signal generation is left undisturbed by RX phase alignment signal generation.Type: GrantFiled: April 12, 2017Date of Patent: May 22, 2018Assignee: Maxlinear Asia Singapore PTE LTDInventors: Mark Hiebert, Jay Chen
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Publication number: 20180138912Abstract: Methods and systems are provided for adaptively configuring voltage-controlled oscillator (VCO) arrays, such as to reduce mismatches among the VCOs. A plurality of voltage-controlled oscillators (VCOs), connected in parallel to a common control input, and with each VCO outputting an oscillating signal based on the common control input and an adjustment input, may be configured to reduce mismatches among the VCOs. The plurality of VCO may be configured by adjusting at least one operational parameter applicable to interconnection paths connecting outputs of the plurality of VCOs; measuring a mismatch between signals at the outputs of the plurality of VCOs with respect to a first signal parameter; and adjusting a first operational parameter applicable to one or more of the plurality of VCOs to reduce mismatch between signals at the outputs of the plurality of VCOs with respect to a first signal parameter.Type: ApplicationFiled: November 14, 2017Publication date: May 17, 2018Inventors: Mark Hiebert, Srinivasa Rao Madala, Hormoz Djahanshahi
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Patent number: 9819349Abstract: A method and system are provided for reducing mismatch between oscillators in an LC VCO array. In an implementation, a method comprises measuring the mismatch between the driver strengths, by measuring the corresponding oscillation amplitudes, and a mismatch between the resonance frequency of each LC VCO in the array of VCOs, and adjusting each LC VCO to reduce the measured amplitude and frequency mismatches. In an implementation, the measuring and adjusting is performed once to calibrate the array of VCOs. In another implementation, the system measures and adjusts the array of VCOs repeatedly. In another implementation, the LC VCO array has a master VCO and a plurality of slave VCOs connected to the master VCO by slave PLLs to reduce phase noise caused by mismatches.Type: GrantFiled: May 27, 2016Date of Patent: November 14, 2017Assignee: MAXLINEAR ASIA SINGAPORE PTE LTD.Inventors: Mark Hiebert, Srinivasa Rao Madala, Hormoz Djahanshahi
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Publication number: 20170222791Abstract: A transmit (TX) signal path circuit in a multiple-input, multiple-output (MIMO) transceiver responsive to a digital front end (DFE) for generating receive (RX) path phase alignment signals is disclosed. A digital up-conversion block uses a first numerically-controlled oscillator (NCO) for generating digital intermediate frequency (IF) signals for ordinary TX signal generation, and a different, second NCO for generating digital IF signals for RX phase alignment signal generation. An RF up-conversion block uses a TX local oscillator (LO) for generating analog RF signals for ordinary TX signal generation, and a different feedback (FB) LO for generating analog RF signals for RX phase alignment signal generation. Thus, phase alignment of the circuitry used for ordinary TX signal generation is left undisturbed by RX phase alignment signal generation.Type: ApplicationFiled: April 12, 2017Publication date: August 3, 2017Inventors: Mark Hiebert, Jay Chen
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Patent number: 9647829Abstract: A transmit (TX) signal path circuit in a multiple-input, multiple-output (MIMO) transceiver responsive to a digital front end (DFE) for generating receive (RX) path phase alignment signals is disclosed. A digital up-conversion block uses a first numerically-controlled oscillator (NCO) for generating digital intermediate frequency (IF) signals for ordinary TX signal generation, and a different, second NCO for generating digital IF signals for RX phase alignment signal generation. An RF up-conversion block uses a TX local oscillator (LO) for generating analog RF signals for ordinary TX signal generation, and a different feedback (FB) LO for generating analog RF signals for RX phase alignment signal generation. Thus, phase alignment of the circuitry used for ordinary TX signal generation is left undisturbed by RX phase alignment signal generation.Type: GrantFiled: April 17, 2015Date of Patent: May 9, 2017Assignee: Maxlinear Asia Singapore Pty Ltd.Inventors: Mark Hiebert, Jay Chen
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Publication number: 20160352341Abstract: A method and system are provided for reducing mismatch between oscillators in an LC VCO array. In an implementation, a method comprises measuring the mismatch between the driver strengths, by measuring the corresponding oscillation amplitudes, and a mismatch between the resonance frequency of each LC VCO in the array of VCOs, and adjusting each LC VCO to reduce the measured amplitude and frequency mismatches. In an implementation, the measuring and adjusting is performed once to calibrate the array of VCOs. In another implementation, the system measures and adjusts the array of VCOs repeatedly. In another implementation, the LC VCO array has a master VCO and a plurality of slave VCOs connected to the master VCO by slave PLLs to reduce phase noise caused by mismatches.Type: ApplicationFiled: May 27, 2016Publication date: December 1, 2016Inventors: Mark HIEBERT, Srinivasa Rao MADALA, Hormoz DJAHANSHAHI
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Patent number: 9356608Abstract: A method and system are provided for reducing mismatch between oscillators in an LC VCO array. In an implementation, a method comprises measuring the mismatch between the driver strengths, by measuring the corresponding oscillation amplitudes, and a mismatch between the resonance frequency of each LC VCO in the array of VCOs, and adjusting each LC VCO to reduce the measured amplitude and frequency mismatches. In an implementation, the measuring and adjusting is performed once to calibrate the array of VCOs. In another implementation, the system measures and adjusts the array of VCOs repeatedly. In another implementation, the LC VCO array has a master VCO and a plurality of slave VCOs connected to the master VCO by slave PLLs to reduce phase noise caused by mismatches.Type: GrantFiled: April 24, 2015Date of Patent: May 31, 2016Assignee: Microsemi Storage Solutions (U.S.), Inc.Inventors: Mark Hiebert, Srinivasa Rao Madala, Hormoz Djahanshahi
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Patent number: 9350399Abstract: A method and apparatus are provided for reducing aliasing in a direct conversion (or zero-IF) radio receiver having high and low frequency paths. According to an implementation, a non-transitory machine-readable memory stores aliasing correlation response data that associates a measured non-aliased signal in a high frequency path and a measured aliased residual of the signal in a low frequency path. A compensator is in communication with the memory to apply aliasing compensation to received signals based on the stored aliasing correlation response data. In an example implementation, the low and high frequency paths are independently optimized for low and high frequency performance, respectively, and have transfer functions that overlap with one another to create a calibration zone used to calibrate the first and second transfer functions.Type: GrantFiled: December 19, 2014Date of Patent: May 24, 2016Assignee: Microsemi Storage Solutions (U.S.), Inc.Inventors: Anthony Eugene Zortea, Mark Hiebert
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Patent number: 9229433Abstract: Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.Type: GrantFiled: November 24, 2014Date of Patent: January 5, 2016Assignee: PMC-SIERRA US, INC.Inventors: Mark Hiebert, Derek J. W. Ho
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Patent number: 9215062Abstract: A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.Type: GrantFiled: July 3, 2015Date of Patent: December 15, 2015Assignee: PMC-Sierra US, Inc.Inventors: Hormoz Djahanshahi, William Michael Lye, Mark Hiebert, Rod Zavari
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Patent number: 9112517Abstract: A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.Type: GrantFiled: June 4, 2014Date of Patent: August 18, 2015Assignee: PMC-Sierra US, Inc.Inventors: William Michael Lye, Hormoz Djahanshahi, Mark Hiebert, Rod Zavari
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Patent number: 9020011Abstract: A transmit (TX) signal path circuit in a multiple-input, multiple-output (MIMO) transceiver responsive to a digital front end (DFE) for generating receive (RX) path phase alignment signals is disclosed. A digital up-conversion block uses a first numerically-controlled oscillator (NCO) for generating digital intermediate frequency (IF) signals for ordinary TX signal generation, and a different, second NCO for generating digital IF signals for RX phase alignment signal generation. An RF up-conversion block uses a TX local oscillator (LO) for generating analog RF signals for ordinary TX signal generation, and a different feedback (FB) LO for generating analog RF signals for RX phase alignment signal generation. Thus, phase alignment of the circuitry used for ordinary TX signal generation is left undisturbed by RX phase alignment signal generation.Type: GrantFiled: May 24, 2013Date of Patent: April 28, 2015Assignee: PMC-Sierra US, Inc.Inventors: Mark Hiebert, Jay Chen
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Patent number: 8866519Abstract: A system and a method for modulating an input signal are provided. The system includes a fractional-N phase locked loop (PLL) for frequency multiplying the input signal by a multiplication factor to generate an output signal. The fractional-N PLL includes an input signal path and a feedback signal path. The system includes a controllable delay line for inserting a linearizing tone into the input signal path or the feedback signal path of the fractional-N PLL.Type: GrantFiled: February 28, 2013Date of Patent: October 21, 2014Assignee: PMC-Sierra US, Inc.Inventor: Mark Hiebert
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Patent number: 8692597Abstract: An integer-N phase-locked loop based clock generator for generating an output clock signal with a frequency N multiples of a reference clock signal, and a method for same, wherein N is a positive integer. The integer-N clock phase-locked loop based generator comprises a reference clock, a voltage controlled oscillator, a clock divider, a first and second phase generator for generating a plurality of phases of the reference clock signal and divided down output clock signal, a plurality of phase frequency detectors and charge pumps. The method comprises generating a reference clock and an output clock signals, generating a plurality of phases of a divided down output clock signal and reference clock signal, comparing the plurality of phases, and changing the frequency of the output clock signal based on the comparison.Type: GrantFiled: March 13, 2013Date of Patent: April 8, 2014Assignee: PMC-Sierra US, Inc.Inventor: Mark Hiebert
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Patent number: 7979041Abstract: The signal strength of an out-of-channel interferer is estimated by measuring the transition density of the sign of the down-converted signal. RF interferers at a higher or lower frequency than the desired RF signal appear as high frequency content in the down-converted signal, thus increasing the likelihood of zero-crossings.Type: GrantFiled: December 7, 2007Date of Patent: July 12, 2011Assignee: PMC-Sierra, Inc.Inventors: Anthony Eugene Zortea, Matthew W. McAdam, Mark Hiebert, Trent Owen McKeen