Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.

Abstract: According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.

Abstract: According to one embodiment, a data processing system includes a plurality of processors, each of the processors being coupled to each of remaining processors via a processor interconnect, a plurality of memory controllers, each memory controller corresponding to one of the processors, a plurality of memory targets, each memory target includes one or more branches and a plurality of memory leaves for storing data, and an Ethernet switch fabric coupled to the memory controllers and the memory targets. When a first of the memory controllers writes data to a first of the memory leaves, the first memory controller sends a cache coherence message to remaining ones of the memory controllers to indicate that the data stored in the first memory leaf has been updated, such that any of the remaining memory controllers can update its cache by fetching the data from the first memory leaf.

Abstract: According to one embodiment, a data processing system includes a plurality of central processing unit (CPU) subsystems, each CPU subsystem having a plurality of CPUs and a plurality of memory controllers, each memory controller corresponding to one of the CPUs, a plurality of memory complexes, each memory complex being associated with one of the CPU subsystems, wherein each memory complex comprises one or more branches, a plurality of memory leaves to store data, wherein each of the branches is coupled to one or more of the memory leaves and to provide access to the data stored in the memory leaves, and a replication interface to automatically replicate data received from one of the CPU subsystems to another one of the memory complexes, wherein the received data is to be stored in one of the memory leaves.

Abstract: A page virtualization table (PVT) and one or more block virtualization tables (BVTs) are maintained. The PVT includes PVT entries, each mapping a logical page number (LPN) to a virtual page number (VPN). Each BVT includes BVT entries, each mapping a virtual block number (VBN) to a physical block number (PBN). A request is received for accessing data stored in one of flash memory devices, the request including a first LPN. A search is performed in the PVT based on the first LPN to locate a first PVT entry to obtain a first VPN from the first PVT entry. A search is performed in a first BVT to locate a first BVT entry based on the VPN to obtain a first PBN from the first BVT entry. An input and output (IO) request is issued based on the first PBN to a flash controller associated with a first flash memory device that stores data corresponding to the first PBN.

Abstract: A system includes a plurality of processors, each being coupled to each of remaining processors via a cluster of processor interconnects. The cluster of processor interconnects form a data distribution network. The system further includes a plurality of roots coupled to the processors, each root corresponding to one of the processors. Each root comprises a memory controller, one or more branches coupled to the memory controller, and a plurality of memory leaves coupled to the branches, each memory leaf having one or more solid state memory devices. Each of the branches is associated with one or more of the memory leaves and provides access to the associated memory leaves. Each of the processors can access any one of the memory leaves via a corresponding branch of any one of the roots over the data distribution network.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: A system includes a plurality of processors, each being coupled to each of remaining processors via a cluster of processor interconnects. The cluster of processor interconnects form a data distribution network. The system further includes a plurality of roots coupled to the processors, each root corresponding to one of the processors. Each root comprises a memory controller, one or more branches coupled to the memory controller, and a plurality of memory leaves coupled to the branches, each memory leaf having one or more solid state memory devices. Each of the branches is associated with one or more of the memory leaves and provides access to the associated memory leaves. Each of the processors can access any one of the memory leaves via a corresponding branch of any one of the roots over the data distribution network.

Abstract: A system includes a collection of central processing units, where each central processing unit is connected to at least one other central processing unit and a root path into at least 10 Tera Bytes of solid state memory resources. Each central processing unit directly accesses solid state memory resources without swapping solid state memory contents into main memory.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: A system includes a collection of central processing units, where each central processing unit is connected to at least one other central processing unit and a root path into at least 10 Tera Bytes of solid state memory resources. Each central processing unit directly accesses solid state memory resources without swapping solid state memory contents into main memory.