Patents by Inventor Mark Hoinkis
Mark Hoinkis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9960052Abstract: Embodiments of the present invention provide methods for patterning a metal layer, such as a copper layer, to form an interconnection structure in semiconductor devices. In one embodiment, a method of patterning a metal layer on a substrate includes (a) supplying an etching gas mixture comprising a hydro-carbon gas into a processing chamber having a substrate disposed therein, the substrate having a metal layer disposed thereon, (b) exposing the metal layer to an ashing gas mixture comprising a hydrogen containing gas to the substrate, and (c) repeatedly performing steps (a) and (b) until desired features are formed in the metal layer. During the patterning process, the substrate temperature may be controlled at greater than 50 degrees Celsius.Type: GrantFiled: April 2, 2014Date of Patent: May 1, 2018Assignee: Applied Materials, Inc.Inventors: Sumit Agarwal, Ann Chien, Chiu-Pien Kuo, Mark Hoinkis, Bradley J. Howard
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Patent number: 9493879Abstract: Methods of patterning conductive layer with a mask are described. The methods include low-ion-mass sputtering of the conductive layer by accelerating (e.g. helium or hydrogen containing ions) toward a substrate which includes the patterned mask and the underlying conductive layer. The sputtering processes described herein selectively remove conductive layers while retaining mask material.Type: GrantFiled: October 1, 2013Date of Patent: November 15, 2016Assignee: Applied Materials, Inc.Inventors: Mark Hoinkis, Hiroyuki Miyazoe, Eric Joseph
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Publication number: 20150287634Abstract: Embodiments of the present invention provide methods for patterning a metal layer, such as a copper layer, to form an interconnection structure in semiconductor devices. In one embodiment, a method of patterning a metal layer on a substrate includes (a) supplying an etching gas mixture comprising a hydro-carbon gas into a processing chamber having a substrate disposed therein, the substrate having a metal layer disposed thereon, (b) exposing the metal layer to an ashing gas mixture comprising a hydrogen containing gas to the substrate, and (c) repeatedly performing steps (a) and (b) until desired features are formed in the metal layer. During the patterning process, the substrate temperature may be controlled at greater than 50 degrees Celsius.Type: ApplicationFiled: April 2, 2014Publication date: October 8, 2015Inventors: Sumit AGARWAL, Ann CHIEN, Chiu-Pien KUO, Mark HOINKIS, Bradley J. HOWARD
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Patent number: 9114438Abstract: Methods of removing copper residue from interior surfaces of an etch process chamber are described. A plasma treatment using halogen-containing precursors transforms the copper residue into halogen-copper complexes. Plasma-excited inert gases are used to desorb the halogen-copper complexes. In this way, the copper residue is removed from the interior surfaces of the etch process chamber.Type: GrantFiled: August 21, 2013Date of Patent: August 25, 2015Assignee: Applied Materials, Inc.Inventors: Mark Hoinkis, Chun Yan, Hiroyuki Miyazoe, Eric Joseph
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Publication number: 20150014152Abstract: Methods of patterning conductive layer with a mask are described. The methods include low-ion-mass sputtering of the conductive layer by accelerating (e.g. helium or hydrogen containing ions) toward a substrate which includes the patterned mask and the underlying conductive layer. The sputtering processes described herein selectively remove conductive layers while retaining mask material.Type: ApplicationFiled: October 1, 2013Publication date: January 15, 2015Applicants: International Business Machines Corporation, Applied Materials, Inc.Inventors: Mark Hoinkis, Hiroyuki Miyazoe, Eric Joseph
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Publication number: 20140345645Abstract: Methods of removing copper residue from interior surfaces of an etch process chamber are described. A plasma treatment using halogen-containing precursors transforms the copper residue into halogen-copper complexes. Plasma-excited inert gases are used to desorb the halogen-copper complexes. In this way, the copper residue is removed from the interior surfaces of the etch process chamber.Type: ApplicationFiled: August 21, 2013Publication date: November 27, 2014Applicants: International Business Machines Corporation, Applied Materials, Inc.Inventors: Mark Hoinkis, Chun Yan, Hiroyuki Miyazoe, Eric Joseph
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Patent number: 8871107Abstract: A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch mask located on a blanker layer of metal or metal alloy. Exposed portions of the blanket layer of metal or metal alloy that are not protected by the etch mask are removed utilizing an etch comprising a plasma that forms a polymeric compound and/or complex which protects a portion of the blanket layer of metal or metal alloy located directly beneath the etch mask during the etch.Type: GrantFiled: March 15, 2013Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Nicholas C. M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe, Mark Hoinkis, Chun Yan
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Publication number: 20140273437Abstract: A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch mask located on a blanker layer of metal or metal alloy. Exposed portions of the blanket layer of metal or metal alloy that are not protected by the etch mask are removed utilizing an etch comprising a plasma that forms a polymeric compound and/or complex which protects a portion of the blanket layer of metal or metal alloy located directly beneath the etch mask during the etch.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicants: APPLIED MATERIALS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicholas C. M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe, Mark Hoinkis, Chun Yan
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Patent number: 7786007Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.Type: GrantFiled: April 7, 2008Date of Patent: August 31, 2010Assignee: Infineon Technologies AGInventors: Mark Hoinkis, Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner, Erdem Kaltalioglu
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Patent number: 7494915Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.Type: GrantFiled: August 9, 2006Date of Patent: February 24, 2009Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor, Erdem Kaltalioglu, Kaushik A. Kumar, Douglas C. La Tulipe, Jr., Jochen Schacht, Andrew H. Simon, Terry A. Spooner, Yun-Yu Wang, Clement H. Wann, Chih-Chao Yang
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Publication number: 20080213993Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.Type: ApplicationFiled: April 7, 2008Publication date: September 4, 2008Inventors: Mark Hoinkis, Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner, Erdem Kaltalioglu
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Patent number: 7368804Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.Type: GrantFiled: May 16, 2003Date of Patent: May 6, 2008Assignee: Infineon Technologies AGInventors: Mark Hoinkis, Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner, Erdem Kaltalioglu
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Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer
Patent number: 7241696Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.Type: GrantFiled: December 11, 2002Date of Patent: July 10, 2007Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Larry Clevenger, Timothy Joseph Dalton, Mark Hoinkis, Steffen K. Kaldor, Kaushik Kumar, Douglas C. La Tulipe, Jr., Soon-Cheon Seo, Andrew Herbert Simon, Yun-Yu Wang, Chih-Chao Yang, Haining Yang -
Patent number: 7241681Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).Type: GrantFiled: January 12, 2006Date of Patent: July 10, 2007Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kaushik Kumar, Lawrence Clevenger, Timothy Dalton, Douglas C. La Tulipe, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht, Andrew H. Simon, Mark Hoinkis, Steffen K. Kaldor, Chih-Chao Yang
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Publication number: 20070059922Abstract: The present invention relates to methods for post-etch, particularly post-RIE, removal of fluorocarbon-based residues from a hybrid dielectric structure. The hybrid dielectric structure contains a first dielectric material, and a line-level dielectric layer containing a second, different dielectric material, and wherein said second, different dielectric material comprises a polymeric thermoset dielectric material having a dielectric constant less than 4. Low energy electron beam or low temperature annealing is utilized by the present invention for removal of the fluorocarbon-based residues from such a hybrid dielectric structure, without damaging the low-k polymeric thermoset dielectric material contained in such a hybrid dielectric structure.Type: ApplicationFiled: September 13, 2005Publication date: March 15, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence Clevenger, Andrew Cowley, Timothy Dalton, Mark Hoinkis, Kaushik Kumar, Douglas La Tulipe, David Rath, Chih-Chao Yang
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Publication number: 20060292852Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.Type: ApplicationFiled: August 9, 2006Publication date: December 28, 2006Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON TECHNOLOGIES NORTH AMERICA CORP.Inventors: Lawrence Clevenger, Andrew Cowley, Timothy Dalton, Mark Hoinkis, Steffen Kaldor, Erdem Kaltalioglu, Kaushik Kumar, Douglas La Tulipe, Jochen Schacht, Andrew Simon, Terry Spooner, Yun-Yu Wang, Clement Wann, Chih-Chao Yang
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Patent number: 7122462Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.Type: GrantFiled: November 21, 2003Date of Patent: October 17, 2006Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor, Erdem Kaltalioglu, Kaushik A. Kumar, Douglas C. La Tulipe, Jr., Jochen Schacht, Andrew H. Simon, Terry A. Spooner, Yun-Yu Wang, Clement H. Wann, Chih-Chao Yang
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Patent number: 7091612Abstract: A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.Type: GrantFiled: October 14, 2003Date of Patent: August 15, 2006Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kaushik Kumar, Timothy Dalton, Larry Clevenger, Andy Cowley, Douglas C. La Tulipe, Mark Hoinkis, Chih-Chao Yang, Yi-Hsiung Lin, Erdem Kaltalioglu, Markus Naujok, Jochen Schacht
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Patent number: 7060619Abstract: Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.Type: GrantFiled: March 4, 2003Date of Patent: June 13, 2006Assignee: Infineon Technologies AGInventors: Andy Cowley, Erdem Kaltalioglu, Mark Hoinkis, Michael Stetter
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Publication number: 20060113278Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).Type: ApplicationFiled: January 12, 2006Publication date: June 1, 2006Inventors: Kaushik Kumar, Lawrence Clevenger, Timothy Dalton, Douglas La Tulipe, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht, Andrew Simon, Mark Hoinkis, Steffen Kaldor, Chih-Chao Yang