Patents by Inventor Mark Horsch

Mark Horsch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240334611
    Abstract: This disclosure describes systems, methods, and devices related to shifting layouts of electronic circuit vias during optical proximity corrections (OPC). A method may include identifying a first metal line, of an electronic circuit, drawn at a first position; identifying a second metal line, of the electronic circuit, drawn at a second position; identifying a via drawn at a third position extending between the first metal line and the second metal line; determining a fourth position to which the first metal line is to move from the first position; determining a fifth position to which the second metal line is to move from the second position; determining, based on the fourth position, the fifth position, a sixth position to which the via is to move from third position; and generating a layout for generating a photomask for the via at the sixth position.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 3, 2024
    Applicant: Intel Corporation
    Inventors: Sunita Thulasi, Dorian Alden, Mark Horsch, A S M Jonayat, Cheng-Tsung Lee, Silvia Liong, Seth Morton, Omar Rahal-Arabi, Prashanth Kumar Siddhamshetty
  • Publication number: 20240220702
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to adjust vias in integrated circuits (ICs) based on machine learning (ML). An example apparatus computes a dimension by which to extend a via based on at least one of a first metal wire in a first layer of the IC above the via, a via-to-via patterning constraint, or a via-to-metal shorting constraint for a second layer of the IC below the via. The example apparatus also computes a shifted position of the via based on at least one of (a) the dimension or (b) a width and a position of a second metal wire below the via, the width and the position predicted by an ML model. Additionally, the example apparatus adjusts a configuration file corresponding to the IC based on at least one of the dimension or the shifted position of the via.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Sunita S. Thulasi, Prashanth Kumar Siddhamshetty, Minjung Kim, Mark Horsch, A S M Jonayat, Anish Shenoy, Cheng-Tsung Lee, Silvia Liong, Dorian Alden, Vipin Agrawal, Anjan Raghunathan, Rusty Wayne Conner