Patents by Inventor Mark Ian A. Arcedera

Mark Ian A. Arcedera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10082966
    Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: September 25, 2018
    Assignee: BiTMICRO LLC
    Inventors: Rolando H. Bruce, Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian A. Arcedera, Ryan C. Chong
  • Patent number: 9484103
    Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: November 1, 2016
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Rolando H. Bruce, Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian A. Arcedera, Ryan C. Chong
  • Patent number: 9099187
    Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: August 4, 2015
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Rolando H. Bruce, Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian A. Arcedera, Ryan C. Chong
  • Patent number: 8560804
    Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: October 15, 2013
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Rolando H. Bruce, Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian A. Arcedera, Ryan C. Chong
  • Publication number: 20110113186
    Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.
    Type: Application
    Filed: September 14, 2010
    Publication date: May 12, 2011
    Applicant: BiTMICRO Networks, Inc.
    Inventors: Rolando H. Bruce, Rayjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian A. Arcedera, Ryan C. Chong
  • Publication number: 20090077306
    Abstract: To optimize memory operations, a mapping table may be used that includes: logical fields representing a plurality of LBA sets, including first and second logical fields for representing respectively first and second LBA sets, the first and second LBA sets each representing a consecutive LBA set; PBA fields representing PBAs, including a first PBA disposed for representing a first access parameter set and a second PBA disposed for representing a second access parameter set, each PBA associated with a physical memory location in a memory store, and these logical fields and PBA fields disposed to associate the first and second LBA sets with the first and second PBAs; and, upon receiving an I/O transaction request associated with the first and second LBA sets, the mapping table causes optimized memory operations to be performed on memory locations respectively associated with the first and second PBAs.
    Type: Application
    Filed: November 25, 2008
    Publication date: March 19, 2009
    Applicant: BITMICRO NETWORKS, INC.
    Inventors: Mark Ian ARCEDERA, Ritchie BABAYLAN, Reyjan LANUZA