Abstract: Aspects of the present disclosure relate to systems and methods for active depth sensing. An example apparatus configured to perform active depth sensing includes a projector. The projector is configured to emit a first distribution of light during a first time and emit a second distribution of light different from the first distribution of light during a second time. A set of final depth values of one or more objects in a scene is based on one or more reflections of the first distribution of light and one or more reflections of the second distribution of light. The projector may include a laser array, and the apparatus may be configured to switch between a first plurality of lasers of the laser array to emit light during the first time and a second plurality of laser to emit light during the second time.

Abstract: Aspects of the present disclosure relate to systems and methods for active depth sensing. An example apparatus configured to perform active depth sensing includes a projector. The projector is configured to emit a first distribution of light during a first time and emit a second distribution of light different from the first distribution of light during a second time. A set of final depth values of one or more objects in a scene is based on one or more reflections of the first distribution of light and one or more reflections of the second distribution of light. The projector may include a laser array, and the apparatus may be configured to switch between a first plurality of lasers of the laser array to emit light during the first time and a second plurality of laser to emit light during the second time.

Abstract: A reconfigurable logic array(RLA) uses pipeline control methods. A do-not-end step signal is communicated to a controller in response to a backpressure condition. In response, a program executing in the RLA is suspended. Source and sink elements are arranged with respective sensors that identify back pressure conditions at interfaces. The source or sink elements communicate a do-not-end step signal to the controller. Local memory interfaces and an interrupt buffer generate similar signals in response to other internal and external conditions. The controller coordinates pipelined control signals with a global counter that issues the control signals with an end-of-step signal broadcast throughout the RLA. When a number of loop iterations is known before execution of the loop instructions, the information is shared with source and sink elements and the controller, which operate accordingly in a limited mode. At appropriate times write-enable inputs of configuration registers are disabled.

Abstract: A reconfigurable instruction cell array is disclosed that includes an array of switch boxes. Each switch box within the array includes a set of I/O ports that are configured to receive a plurality of input channels from neighboring switch boxes in the array. Within a switch box, one of the I/O ports conditionally selects from the input channels received by the remaining I/O ports in the switch box to form a plurality of output channels to be driven to a neighboring switch box in the array.

Abstract: A reconfigurable logic array(RLA) uses pipeline control methods. A do-not-end step signal is communicated to a controller in response to a backpressure condition. In response, a program executing in the RLA is suspended. Source and sink elements are arranged with respective sensors that identify back pressure conditions at interfaces. The source or sink elements communicate a do-not-end step signal to the controller. Local memory interfacesand an interrupt buffer generate similar signals in response to other internal and external conditions. The controller coordinates pipelined control signals with a global counter that issues the control signals with an end-of-step signal broadcast throughout the RLA. When a number of loop iterations isknown before execution of the loop instructions, the information is shared with source and sink elements and the controller, which operate accordingly in a limited mode. At appropriate timeswrite-enable inputs of configuration registers are disabled.

Abstract: A reconfigurable instruction cell array is disclosed that includes an array of switch boxes. Each switch box within the array includes a set of I/O ports that are configured to receive a plurality of input channels from neighboring switch boxes in the array. Within a switch box, one of the I/O ports conditionally selects from the input channels received by the remaining I/O ports in the switch box to form a plurality of output channels to be driven to a neighboring switch box in the array.