Abstract: A method for sensing granular media characteristics. A coil is provided and wound around a pipe for containing granular media. A driver provides an oscillating current through the coil and the driver maintains a constant voltage. A table lists known properties of inductance and impedance for media of a predetermined material and having a particular size. The media is retained in the coil and the drive drives the oscillating current when media is present in the coil. The inductance and impedance are measured to determine the material of the media and the size of the media.

Abstract: A shot peening flow rate control that is useful for non-ferrous shot peening media. The control has an inlet for receiving media and an orifice through which the media may pass that is in communication with the inlet. A valve selectively blocks the orifice. The valve has a spindle that is guided for axial movement between an open and closed position. The closed position blocks the orifice and the open position places the spindle spaced from the orifice to allow media to flow through the orifice. A flow sensor has a deflectable member that extends into a flow path of media leaving the orifice. In response to increasing or decreasing flow of the media through the flow path the deflectable member will deflect more or less. A sensing device measures the deflection in the deflectable member and generates an electrical signal that varies in response to deflection in the deflectable member.

Abstract: A shot peening flow rate control that is useful for non-ferrous shot peening media. The control has an inlet for receiving media and an orifice through which the media may pass that is in communication with the inlet. A valve selectively blocks the orifice. The valve has a spindle that is guided for axial movement between an open and closed position. The closed position blocks the orifice and the open position places the spindle spaced from the orifice to allow media to flow through the orifice. A flow sensor has a deflectable member that extends into a flow path of media leaving the orifice. In response to increasing or decreasing flow of the media through the flow path the deflectable member will deflect more or less. A sensing device measures the deflection in the deflectable member and generates an electrical signal that varies in response to deflection in the deflectable member.

Abstract: This disclosure relates to systems and methods that facilitate restricting operation of a client device to parent approved content.

Abstract: A device having a resistive memory element, a control device, a digit line and a sensing circuit. The sensing circuit is configured to sense a voltage correlative to a resistance state of the resistive memory element. The sensing circuit if further configured to sense the voltage correlative to the resistance state after a waiting period that is less than or equal to the product of a capacitance of a digit line and a total resistance of the control device.

Abstract: A device having a resistive memory element, a control device, a digit line and a sensing circuit. The sensing circuit is configured to sense a voltage correlative to a resistance state of the resistive memory element. The sensing circuit if further configured to sense the voltage correlative to the resistance state after a waiting period that is less than or equal to the product of a capacitance of a digit line and a total resistance of the control device.

Abstract: A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power circuits. In accordance with a second exemplary embodiment, the power circuits are coupled to the bit lines and replace the reference circuit in a manner to improve sensing margin.

Abstract: A system having a memory cell. In certain embodiments, the memory cell includes a resistive memory element, an access transistor having a gate, a first terminal, and a second terminal, and a control transistor having a gate, a first terminal, and a second terminal. The first terminal of the access transistor may be coupled to the resistive memory element, and the gate of the access transistor may be coupled to the gate of the control transistor. Additionally, the first terminal of the control transistor may be coupled to the resistive memory element.

Abstract: A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power circuits. In accordance with a second exemplary embodiment, the power circuits are coupled to the bit lines and replace the reference circuit in a manner to improve sensing margin.

Abstract: A system having a memory cell. In certain embodiments, the memory cell includes a resistive memory element, an access transistor having a gate, a first terminal, and a second terminal, and a control transistor having a gate, a first terminal, and a second terminal. The first terminal of the access transistor may be coupled to the resistive memory element, and the gate of the access transistor may be coupled to the gate of the control transistor. Additionally, the first terminal of the control transistor may be coupled to the resistive memory element.

Abstract: A system having a memory cell. In certain embodiments, the memory cell includes a resistive memory element, an access transistor having a gate, a first terminal, and a second terminal, and a control transistor having a gate, a first terminal, and a second terminal. The first terminal of the access transistor may be coupled to the resistive memory element, and the gate of the access transistor may be coupled to the gate of the control transistor. Additionally, the first terminal of the control transistor may be coupled to the resistive memory element.

Abstract: A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power circuits. In accordance with a second exemplary embodiment, the power circuits are coupled to the bit lines and replace the reference circuit in a manner to improve sensing margin.

Abstract: A system having a memory cell. In certain embodiments, the memory cell includes a resistive memory element, an access transistor having a gate, a first terminal, and a second terminal, and a control transistor having a gate, a first terminal, and a second terminal. The first terminal of the access transistor may be coupled to the resistive memory element, and the gate of the access transistor may be coupled to the gate of the control transistor. Additionally, the first terminal of the control transistor may be coupled to the resistive memory element.

Abstract: A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power circuits. In accordance with a second exemplary embodiment, the power circuits are coupled to the bit lines and replace the reference circuit in a manner to improve sensing margin.

Abstract: A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power circuits. In accordance with a second exemplary embodiment, the power circuits are coupled to the bit lines and replace the reference circuit in a manner to improve sensing margin.

Abstract: A resistance variable memory device such as e.g., a PCRAM memory device, with either a 4T (transistor) or 2T memory cell configuration and either a dual cell plate or word line configuration. The device includes additional circuitry configured to write or erase addressed cells while keeping the voltage across non-addressed cells at approximately 0V. The device also includes circuitry that reads the addressed cells in a manner that increases the sensing window without causing the potential across the cell to be greater than approximately 200 mV. The device may also sense the state of its addressed cells closer in time to when the cells are accessed, in comparison to typical sensing techniques.

Abstract: A resistance variable memory device such as e.g., a PCRAM memory device, with either a 4T (transistor) or 2T memory cell configuration and either a dual cell plate or word line configuration. The device includes additional circuitry configured to write or erase addressed cells while keeping the voltage across non-addressed cells at approximately 0V. The device also includes circuitry that reads the addressed cells in a manner that increases the sensing window without causing the potential across the cell to be greater than approximately 200 mV. The device may also sense the state of its addressed cells closer in time to when the cells are accessed, in comparison to typical sensing techniques.

Abstract: A resistance variable memory device such as e.g., a PCRAM memory device, with either a 4T (transistor) or 2T memory cell configuration and either a dual cell plate or word line configuration. The device includes additional circuitry configured to write or erase addressed cells while keeping the voltage across non-addressed cells at approximately 0V. The device also includes circuitry that reads the addressed cells in a manner that increases the sensing window without causing the potential across the cell to be greater than approximately 200 mV. The device may also sense the state of its addressed cells closer in time to when the cells are accessed, in comparison to typical sensing techniques.

Abstract: A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power circuits. In accordance with a second exemplary embodiment, the power circuits are coupled to the bit lines and replace the reference circuit in a manner to improve sensing margin.