Patents by Inventor Mark J. Bailey
Mark J. Bailey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118500Abstract: A system comprises an optical fiber, a manipulator assembly, and a control unit. The manipulator assembly comprises a chassis, an optical fiber cleaning assembly housed within the chassis, and a drive mechanism housed within the chassis. The optical fiber cleaning assembly comprises a cleaning tape, a first spool on which the cleaning tape is wound, and a second spool onto which the cleaning tape is drawn after use. The drive mechanism is configured to advance the cleaning tape from the first spool to the second spool such that a portion of the cleaning tape wipes a face of the optical fiber. The control unit is configured to control the drive mechanism to advance the cleaning tape.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Inventors: Matthew D. Rohr Daniel, Troy K. Adebar, David W. Bailey, Stephen J. Blumenkranz, Edward P. Donlon, Mark E. Froggatt, Christopher M. Major, Randall L. Schlesinger
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Publication number: 20100025864Abstract: A wirebond interconnect structure, having ground pads and signal pads, to which wirebonds are electrically coupled, disposed on a component, is provided and includes a first coating to insulate at least the wirebonds and the signal pads with at least the ground pads exposed, and a second coating, surrounding the first coating, in electrical communication with the ground pads. The first coating is sufficiently thick to achieve a consistent characteristic impedance when the second coating is applied.Type: ApplicationFiled: July 31, 2008Publication date: February 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark J. Bailey, Gerald K. Bartley, Darryl J. Becker, Paul E. Dahlen, Philip R. Germann, Andrew B. Maki, Mark O. Maxson
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Publication number: 20090268422Abstract: A scalable electronic package assembly for memory devices and other terminated bus structures is disclosed. The scalable electronic package assembly includes a first electronic carrier and a second electronic carrier. The first electronic carrier includes a first set of electronic devices controlled by a controller. The second electronic carrier includes a second set of electronic devices that are also controlled by the controller on the first electronic carrier. The second electronic carrier is electrically connected to the first electronic carrier via multiple solder columns. The second electronic carrier is physically stacked on top of the first electronic carrier via an insulator.Type: ApplicationFiled: April 29, 2008Publication date: October 29, 2009Inventors: Mark J. Bailey, Gerald K. Bartley, Richard B. Ericson, Wesley D. Martin, Benjamin W. Mashak, Trevor J. Timpane
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Publication number: 20090085155Abstract: A method of package-to-board impedance matching for high speed integrated circuits (ICs). Multiple solder balls are attached to an IC package. The IC package includes multiple conductive interconnect layers, where one of the conductive interconnect layers is coupled to one or more of the multiple solder balls. Multiple vias are coupled between different conductive interconnect layers. An inductive element is coupled between an interconnect lead and a via land in the conductive interconnect layer within the IC package. The physical layout dimensions of the inductive element are configured such that the inductive element provides an inductance value that is sufficient to offset a parasitic capacitance provided by the conductive interconnect layers and the solder balls. The inductive element may be a bond wire, an inductive interconnect, or a spiral interconnect.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Inventors: Mark J. Bailey, Todd A. Cannon, Haitian Hu, Nanju Na, Katsuyuki Yonehara, Deborah E. Zwitter
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Patent number: 7476040Abstract: The present invention relates to an optical sub-assembly, i.e. a receiver optical subassembly or a transmitter optical sub-assembly, for use in an optical transceiver device. The optical sub-assembly according to the present invention includes a hermetic ceramic package with a multi-layer ceramic structure providing a unique RF signal and ground structure providing a controlled signal impedance to achieve high signal transmission quality.Type: GrantFiled: January 31, 2005Date of Patent: January 13, 2009Assignee: JDS Uniphase CorporationInventors: Jeffrey Zack, Craig A. Young, Anand Shukla, Wei Xu, William K. Hogan, David Peter Gaio, Chris Hart, Philip Deane, Mark J. Bailey, Martin A. Helfand
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Patent number: 7377036Abstract: A fuel nozzle assembly for a gas turbine includes a plurality of circumferentially spaced vanes with holes for flowing fuel from plenums within the vanes through holes in the vane walls for premixing with air. To tune the nozzle assembly, the holes are resized by reforming the existing holes to a predetermined hole size, securing plugs into the holes, and forming holes through at least certain of the plugs to diameters less than the diameter of the existing holes.Type: GrantFiled: October 5, 2004Date of Patent: May 27, 2008Assignee: General Electric CompanyInventors: Jere A. Johnson, Mark J. Bailey, Mark D. Pezzutti, James Christopher Monaghan, Ron Souther, Robert R. Berry
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Patent number: 7001151Abstract: A tip cap for a turbine blade. The tip cap may include a HS-188 sheet material with a thickness of less than about 0.079 inches (about 2 millimeters) and a number of holes positioned in the sheet material.Type: GrantFiled: March 2, 2004Date of Patent: February 21, 2006Assignee: General Electric CompanyInventors: John Z. Wang, Mark J. Bailey, Robert R. Berry, Emilio Fernandez
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Patent number: 6734369Abstract: A surface laminar circuit board includes an insulating layer, and a signal ground conductive layer disposed on an upper surface of the insulating layer. The conductive layer has a hole formed therein. A photosensitive dielectric layer is disposed on an upper surface of the signal ground conductive layer. The dielectric layer has a photo micro-via formed therein. A signal trace is disposed on the photosensitive dielectric layer, and is electrically coupled with the signal ground conductive layer by way of the photo micro-via. A conductive pad is provided, which has a majority thereof within an area defined by an outer periphery of the hole. The conductive pad is electrically coupled with the signal trace. A surface mounted component is mounted on the conductive pad.Type: GrantFiled: August 31, 2000Date of Patent: May 11, 2004Assignee: International Business Machines CorporationInventors: Mark J. Bailey, Michael John Shea, Gerald Wayne Swift
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Patent number: 6594893Abstract: A surface laminar circuit board includes an insulating layer, and a signal ground conductive layer disposed on an upper surface of the insulating layer. The conductive layer has a hole formed therein. A photosensitive dielectric layer is disposed on an upper surface of the signal ground conductive layer. The dielectric layer has a photo micro-via formed therein. A signal trace is disposed on the photosensitive dielectric layer, and is electrically coupled with the signal ground conductive layer by way of the photo micro-via. A conductive pad is provided, which has a majority thereof within an area defined by an outer periphery of the hole. The conductive pad is electrically coupled with the signal trace. A surface mounted component is mounted on the conductive pad.Type: GrantFiled: September 18, 2001Date of Patent: July 22, 2003Assignee: International Business Machines CorporationInventors: Mark J. Bailey, Michael John Shea, Gerald Wayne Swift
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Publication number: 20020131724Abstract: A high frequency matching method and silicon optical bench employing a high frequency matching network are provided. The silicon optical bench comprises a silicon wafer defining a structure for precisely locating an electro-optical component. A predefined metal trace pattern is formed on a surface of the silicon wafer. The predefined metal trace pattern at least one electrical device, such as a thin film resistor, a capacitor or an inductor; or a selected combination of at least one thin film resistor, capacitor or inductor formed at selected predefined locations within the predefined metal trace pattern. The predefined metal trace pattern provides a high frequency impedance matching network for connection with the electro-optical component. The predefined metal trace pattern includes a plurality of selected widths within the predefined metal trace pattern. The widths are selectively provided for changing inductance within the predefined metal trace pattern.Type: ApplicationFiled: March 15, 2001Publication date: September 19, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark J. Bailey, David Peter Gaio, William K. Hogan, Gerald Wayne Swift
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Publication number: 20020023776Abstract: A surface laminar circuit board includes an insulating layer, and a signal ground conductive layer disposed on an upper surface of the insulating layer. The conductive layer has a hole formed therein. A photosensitive dielectric layer is disposed on an upper surface of the signal ground conductive layer. The dielectric layer has a photo micro-via formed therein. A signal trace is disposed on the photosensitive dielectric layer, and is electrically coupled with the signal ground conductive layer by way of the photo micro-via. A conductive pad is provided, which has a majority thereof within an area defined by an outer periphery of the hole. The conductive pad is electrically coupled with the signal trace. A surface mounted component is mounted on the conductive pad.Type: ApplicationFiled: September 18, 2001Publication date: February 28, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark J. Bailey, Michael John Shea, Gerald Wayne Swift
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Patent number: 5318402Abstract: A spacer band for maintaining uniform spacing between adjacent compressor liner segments comprising two segments having a plurality of locking fingers extending from the band for engaging the casing at both ends of the liner segments and in the middle of the segments. The spacer band is located in a vertical channel located along an edge of each liner segment. The vertical channel is defined by a plurality of vertical flanges and a horizontal flange located on the edge of each liner segment. The horizontal flange has notches for receiving said locking fingers.Type: GrantFiled: September 21, 1992Date of Patent: June 7, 1994Assignee: General Electric CompanyInventors: Mark J. Bailey, Kurt J. Bonner
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Patent number: 5310317Abstract: A gas turbine engine rotor blade includes an airfoil joined to a dovetail. The dovetail includes a shank from which extends two pairs of dovetail tangs being defined by a bifurcating slot disposed therebetween. The dovetail is configured for retention in a complementary dovetail groove in a rotor disk with the bifurcating slot remaining empty for reducing weight of the blade while transferring centrifugal loads from the blade to the rotor disk.Type: GrantFiled: August 11, 1992Date of Patent: May 10, 1994Assignee: General Electric CompanyInventors: Mark J. Bailey, Robert K. Mitchell, Jr.
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Patent number: 5271718Abstract: A rotor blade for a gas turbine engine includes an airfoil, platform and dovetail. The platform has top and bottom surfaces, with a plurality of pockets disposed in the bottom surface for reducing weight of the platform, with the pockets defining a plurality of continuous beams extending along the platform which provide structural stiffness to the platform to avoid resonance vibration thereof during operation.Type: GrantFiled: August 11, 1992Date of Patent: December 21, 1993Assignee: General Electric CompanyInventors: Robert K. Mitchell, Jr., Mark J. Bailey
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Patent number: 5232346Abstract: A platform spacer is joinable to a rotor disk between adjacent rotor blades having dovetails retained in a circumferential dovetail groove therein. The spacer includes a platform having a flat upper surface sized for abutting adjacent blade platforms to form an inner flowpath, and first and second hooks extending downwardly from the platform lower surface. The first and second hooks are configured for insertion radially inwardly through first and second loading recesses in the rotor disk for retention thereto.Type: GrantFiled: August 11, 1992Date of Patent: August 3, 1993Assignee: General Electric CompanyInventors: Robert K. Mitchell, Jr., Mark J. Bailey