Patents by Inventor Mark J. Chambers
Mark J. Chambers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7508272Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.Type: GrantFiled: September 24, 2007Date of Patent: March 24, 2009Assignee: Broadcom CorporationInventors: Siavash Fallahi, Chun Ying Chen, Mark J. Chambers
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Patent number: 7274260Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.Type: GrantFiled: August 1, 2006Date of Patent: September 25, 2007Assignee: Broadcom CorporationInventors: Siavash Fallahi, Chun Ying Chen, Mark J. Chambers
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Patent number: 7161781Abstract: A signal driving system generates an output swinging between a first power supply (e.g., about 1.2 Volts), powering first and second drivers, and a second power supply (e.g., about 3.3 Volts), powering a first current mirror. The second power supply is generated external to the signal driving system and is used to allow for a desired common-mode differential output signal range. However, the second power supply produces voltage at a level above a rating of the devices in the signal driving system. Therefore, protection devices are used to protect the elements of the signal driving system from the second power supply. Accordingly, through use of the signal driving system of the present invention, a high voltage current mode driver can operate in a low voltage process without damaging the devices in the signal driving system.Type: GrantFiled: September 12, 2003Date of Patent: January 9, 2007Assignee: Broadcom CorporationInventors: Josephus A. E. P. van Engelen, Yee Ling Cheung, Mark J Chambers, Darwin Cheung
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Patent number: 7116176Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.Type: GrantFiled: June 15, 2004Date of Patent: October 3, 2006Assignee: Broadcom CorporationInventors: Siavash Fallahi, Chun Ying Chen, Mark J. Chambers
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Patent number: 6963245Abstract: A system and method are used to accelerate settling or steady state of an amplifier in an amplifier system. This is used to ensure the amplifier reaches steady-state within a specified time period from stand-by or another state without using more current than is needed for steady-state. A comparator in a common-mode feedback system compares a desired amplifier output signal to one or more nodes of the amplifier. A result of the comparison is compared to a threshold value using a comparator in a settling acceleration system. If the result crosses the threshold, a controller turns on a driver in the settling acceleration system. The driver pulls on one or more nodes of the amplifier, which, along with a driver in the amplifier system pulling on the node, quickly brings the amplifier to settling or steady state.Type: GrantFiled: September 3, 2003Date of Patent: November 8, 2005Assignee: Broadcom CorporationInventors: Josephus A. E. P. van Engelen, Kwang Young Kim, Mark J. Chambers
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Patent number: 6922109Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.Type: GrantFiled: April 25, 2002Date of Patent: July 26, 2005Assignee: Broadcom CorporationInventors: Siavash Fallahi, Chun Ying Chen, Mark J. Chambers
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Patent number: 6868431Abstract: A Finite Impulse Response (FIR) filter circuit (60) includes delay elements (63, 64, 66), multipliers (71, 72, 73, 74), a summing device (78), and a digital integrator (69) at the output of the FIR filter circuit (60). A method for processing data using the FIR filter circuit (60) includes differentially encoding data prior to storing or processing of the data. The method provides a technique for compressing data since less memory is needed to store derivative data. The method further includes integrating the derivative data using the digital integrator (69) to decompress the derivative data.Type: GrantFiled: October 25, 1999Date of Patent: March 15, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Jesus L. Finol, Mark J. Chambers, Albert H. Higashi, James B. Phillips
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Patent number: 6853510Abstract: A variable gain amplifier to output a differential output signal includes an input circuit to input a differential input signal, a buffer circuit to buffer the differential output signal to a common mode voltage, a compensation circuit to compensate the differential output signal to prevent variation in the differential output signal, and a comparison circuit to compare the common mode voltage to a predetermined voltage and to adjust the common mode voltage to equal the predetermined voltage.Type: GrantFiled: October 3, 2001Date of Patent: February 8, 2005Assignee: Texas Instruments IncorporatedInventors: Alan I. Chaiken, Mark J. Chambers
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Publication number: 20040239432Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.Type: ApplicationFiled: June 15, 2004Publication date: December 2, 2004Inventors: Siavash Fallahi, Chun Ying Chen, Mark J. Chambers
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Publication number: 20030184646Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.Type: ApplicationFiled: April 25, 2002Publication date: October 2, 2003Applicant: Broadcom CorporationInventors: Siavash Fallahi, Chun Ying Chen, Mark J. Chambers
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Patent number: 6510012Abstract: An asymmetry correction circuit for correcting an asymmetry signal includes a first transconductance circuit for transforming the asymmetry signal to a bias current in a first current path, a second transconductance circuit to form the bias current in a second current path, and a feed-forward circuit for transforming the asymmetry signal to a positive difference current and a negative difference current.Type: GrantFiled: July 28, 2000Date of Patent: January 21, 2003Assignee: Texas Instruments IncorporatedInventors: Alan I. Chaiken, Mark J. Chambers, Jose O. Perez
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Publication number: 20020122265Abstract: An offset correction circuit to correct DC offset in accordance with a data rate includes a detection circuit to detect a thermal asperity signal and a filter circuit to respond to the thermal asperity signal in accordance with the data rate.Type: ApplicationFiled: July 10, 2001Publication date: September 5, 2002Inventors: Mark J. Chambers, Scott A. Kaylor, Jose O. Perez, Alan I. Chaiken
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Publication number: 20020054445Abstract: A variable gain amplifier to output a differential output signal includes an input circuit to input a differential input signal, a buffer circuit to buffer the differential output signal to a common mode voltage, a compensation circuit to compensate the differential output signal to prevent variation in the differential output signal, and a comparison circuit to compare the common mode voltage to a predetermined voltage and to adjust the common mode voltage to equal the predetermined voltage.Type: ApplicationFiled: October 3, 2001Publication date: May 9, 2002Inventors: Alan I. Chaiken, Mark J. Chambers
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Publication number: 20020048109Abstract: A dB gain amplifier for providing a levelized output signal includes a first transconductance circuit to output a first current in a first current path, a second transconductance circuit to output a second current in a second current path, a first current mirror to control the first current in the first current path, a second current mirror to control the second current in the second current path, and a DAC circuit to control the first and second current mirrors piecewise linearly.Type: ApplicationFiled: August 30, 2001Publication date: April 25, 2002Inventors: Alan I. Chaiken, Mark J. Chambers, Jose O. Perez
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Patent number: 5901347Abstract: A method and apparatus provides control of the gain of an input amplifier (306) in a radio receiver (300), such as in a radiotelephone handset (104). The radio receiver (300) includes an automatic gain control circuit (318). The automatic gain control circuit (318) includes a timer circuit (370) which provides asynchronous, digital automatic gain control circuit to perform a coarse gain adjustment. The automatic gain control circuit (318) further includes an integrator (366) which provides analog automatic gain control for providing remaining needed gain regulation. The automatic gain control circuit (318) provides substantial reduction in input signal acquisition time for the radio receiver (300).Type: GrantFiled: January 17, 1996Date of Patent: May 4, 1999Assignee: Motorola, Inc.Inventors: Mark J. Chambers, Jaime A. Borras, S. Hossein Beladi
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Patent number: 5832370Abstract: A transmitter (300) sends a transmitted current (I.sub.203, I.sub.204) along a transmit signal path (203, 204) to a receiver (400) having a low input impedance. The receiver includes a transistor structure (402, 404) that amplifies the transmitted current and feeds it back to the input of the receiver to maintain the low input impedance and a substantially constant voltage on the transmit signal path. The substantially constant voltage at the input of the receiver avoids interference with other circuits (206, 208) located along the transmit signal path.Type: GrantFiled: September 26, 1996Date of Patent: November 3, 1998Assignee: Motorola, Inc.Inventors: Jesus S. Pena-Finol, Mark J. Chambers, Erica G. Miller, Philippe Gorisse
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Patent number: 5625316Abstract: A tuning circuit (202) uses a precision current reference (Iref) along with an analog-to-digital converter (218) to produce a digital output (228) to represent variations of internal resistance values. The precision current reference (Iref) is fed to an internal tuning resistor (R210) in order to provide an analog voltage signal to the analog-to-digital converter (218). The analog voltage signal changes in accordance with the variations in the tuning resistor value over process and temperature. The digital output (228) controls programmable capacitor arrays (C220, C222) which are included in the tuning circuit (202) as well as in an active RC filter (208) whose bandwidth is controlled by the programmable capacitor arrays (C220, C222) and internal resistors (R212, R214, R216).Type: GrantFiled: July 1, 1994Date of Patent: April 29, 1997Assignee: Motorola, Inc.Inventors: Mark J. Chambers, Jesus P. Finol, James B. Phillips
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Patent number: 5598129Abstract: An operational transconductance amplifier (500) includes an input stage (502) having a first and second amplifiers (504, 508) driving class-AB, push-pull amplifiers (506, 510). The input stage (502) receives a differential input signal at first and second amplifier inputs (528, 540). The push-pull amplifiers (506, 510) establish differential currents in a transconductance-setting resistor (512), thereby eliminating the need for static current sources. The biasing levels established by the first and second amplifiers (504, 508) to drive the push-pull amplifiers (506, 510) also control a current source (514). Currents from the current source (514) are summed and provided to amplifier outputs (594, 596).Type: GrantFiled: August 24, 1995Date of Patent: January 28, 1997Assignee: Motorola, Inc.Inventor: Mark J. Chambers
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Patent number: 5530399Abstract: A transconductance scaling circuit (500) includes an operational transconductance amplifier (504) having a tunable voltage, V.sub.tune2. A feedback loop controls the tunable voltage, V.sub.tune2, in response to the digital programming of the transconductance amplifier (504) and provides the tunable voltage as a current scaling output.Type: GrantFiled: December 27, 1994Date of Patent: June 25, 1996Assignee: Motorola, Inc.Inventors: Mark J. Chambers, James B. Phillips
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Patent number: 5465409Abstract: A radio having two architectural platforms integrated in one integrated circuit (IC). A synthesizer controller (312) selects between an offset local oscillator (LO) synthesizer (318) and a second LO synthesizer (316) to provide a common architecture for either an Frequency Division Duplex (FDD) or Time Division Duplex (TDD) system design while providing isolation between the two frequency sources. An offset LO signal (319) is translated to an isolated LO signal 310 and combined with a main LO signal (322) to provide the FDD platform. A second LO signal (314) is translated into the isolated LO signal 310 and combined with the main LO signal (322) to provide the TDD platform. The second LO synthesizer signal (314) is common to both systems in the receive mode.Type: GrantFiled: March 7, 1994Date of Patent: November 7, 1995Assignee: Motorola, Inc.Inventors: Jaime A. Borras, Mark J. Chambers, Jesus S. Pena Finol, Armando J. Gonzalez, Cesar W. Carralero, Sayed H. Beladi, Levent Y. Erbora