Patents by Inventor Mark J. Cullen

Mark J. Cullen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5332653
    Abstract: A process for forming a conductive region without photoresist-related reflective notching damage has a starting step (23) wherein a photoresist layer is formed over a conductive layer (34). The photoresist layer is used to mask the conductive layer. The photoresist layer is lithographically processed and chemically developed to form a masking photoresist region (38) overlying the conductive layer (34). The masking photoresist region has a sidewall and has a reflective notch which results from the lithographic processing. A hardening step, performed in-situ with a plurality of conductive layer etch steps, is used to form an etch-resistant polymer layer (40) on the photoresist sidewalls and on the reflective notch. The conductive layer (34) is etched after the formation of the polymer layer (40) to form a conductive region. The polymer layer (40) reduces an etch rate of the reflective notch and the photoresist sidewall so that the conductive region is formed having no reflective notching etch damage.
    Type: Grant
    Filed: July 1, 1992
    Date of Patent: July 26, 1994
    Assignee: Motorola, Inc.
    Inventors: Mark J. Cullen, Sean Hunkler
  • Patent number: 4994404
    Abstract: A process is disclosed for the formation of an LDD structure in an MOS transistor having a reduced mask count and providing high integrity source/drain junctions. In accordance with one embodiment of the invention an MOS transistor is formed having a gate dielectric overlying an active region of the substrate. A transistor gate is formed in a central portion of the active region and an oxidation layer is formed over the active region and the transistor gate. A lightly-doped source/drain region is formed which is self aligned to the transistor gate. A conformal layer of an oxygen reactive material is formed overlying the transistor gate and the active region. The oxygen reactive material is anisotropically etched in a oxygen plasma reactive ion etch to form a sidewall spacer on the edge the transistor gate. The oxygen reactive ion etch does not penetrate the oxidation layer overlying the active region. A heavily-doped source/drain region is formed which is self aligned to the edge of the sidewall spacer.
    Type: Grant
    Filed: August 28, 1989
    Date of Patent: February 19, 1991
    Assignee: Motorola, Inc.
    Inventors: David Y. Sheng, Yasunobu Kosa, Andrew J. Urquhart, Mark J. Cullen