Abstract: An improved symbol synchronization circuit is provided for generting a clock signal in a receiver having an input signal comprising a stream of symbols at a symbol rate of f.sub.symbol. According to the invention, a correlator is provided that operates on a multiplicity (k) of multi-phase signals, .phi..sub.1 -.phi..sub.k, each signal more or less synchronized with the stream of symbols and each having a frequency f.sub.clock generally equal to a multiple of f.sub.symbol. Based on the current synchronization of each signal .phi..sub.1 -.phi..sub.k with the stream of symbols, and also based on the past history of the synchronization of each signal with the stream of symbols, one member from the group of signals .phi..sub.1 -.phi..sub.k is periodically selected as the clock signal. This selected clock signal is then delayed to compensate for the drift between f.sub.symbol and f.sub.clock.