Patents by Inventor Mark J. Mercer

Mark J. Mercer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6781450
    Abstract: The present invention is related to glitch reduction of the output of an auto-zero amplifier. The auto-zero amplifier may be used in a voltage regulator, and the glitch reduction in the auto-zero amplifier will result in reduced output ripple. The auto-zero amplifier stores an input offset during an auto-zero phase, so that the input offset can be corrected during an amplification phase. During the amplification phase, the gate-drain voltage of a first transistor is sampled onto a capacitor. During the auto-zero phase, the capacitor is used to maintain the same voltage across the gate-drain voltage of the first transistor that was present during the amplification phase. The capacitor maintains the gate-drain voltage during the auto-zero phase in order to compensate for the large step in voltage that would otherwise occur.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: August 24, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Mark J. Mercer, Paul Ranucci
  • Patent number: 6329804
    Abstract: A method and apparatus for trimming the level and slope in a voltage reference using current-switching DACs to inject small correction currents into or draw currents from the voltage reference circuit. Each DAC is controlled via a programmable non-volatile memory, which can be programmed after final packaging. Thus, the present technique enables trimming the voltage reference circuit after the circuit has been packaged. For the slope trim, the current is injected into or drawn from one side or the other of the band-gap core cell. The level trim DAC sources a correction current into or sinks a correction current from the resistor chain that sets the voltage level at the base of the transistors in the band-gap core. The level and slope trim DACs generate currents that are precise multiples of the currents through the resistors being trimmed. Thus the corrections are invariant with process and temperature, the necessary trim range is minimized, and the shape of the remaining error (curvature) is not altered.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: December 11, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Mark J. Mercer
  • Patent number: 6225782
    Abstract: A circuit for providing hi-Z charging of a deeply discharged battery includes a load simulator circuit to provide a charging load resistance even when the battery has been discharged to 0V. The load simulator circuit includes a transistor connected in series with the battery. A logic circuit detects when the battery voltage is below a minimum threshold voltage and instructs a voltage control circuit to provide a constant voltage across the battery and the load simulator circuit. The logic circuit also applies the output of a current control circuit to the gate terminal of the transistor, enabling the current control circuit to regulate the total resistive load of the battery-transistor pair and thus maintain a constant hi-Z charge current across the battery.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: May 1, 2001
    Assignee: National Semiconductor Corporation
    Inventors: Mark J. Mercer, Stuart B. Shacter
  • Patent number: 6215291
    Abstract: A control circuit is provided to minimize the charging cycle time of a battery charging system by maximizing the length of time that high constant charging current is applied to a discharged battery. The control circuit includes a constant current (CC) error amplifier, a constant voltage (CV) error amplifier, an output amplifier, and two pole-splitting compensation networks. The control circuit works in conjunction with a power source to charge a secondary battery. The pole-splitting compensation networks allow the CC, CV, and output amplifiers to be configured for high gain, without sacrificing output stability. The control circuit provides a sharp transition between the CC mode and CV mode of operation. In the CC mode, fast bulk battery charging is provided. In the CV mode, the control circuit initially provides a “top-off” charge to the battery and subsequently safely maintains the battery at its fully charged state.
    Type: Grant
    Filed: April 17, 2000
    Date of Patent: April 10, 2001
    Assignee: National Semiconductor Incorporated
    Inventor: Mark J. Mercer
  • Patent number: 6201379
    Abstract: A CMOS voltage reference comprises a band-gap core, a primary amplifier and a “nulling” amplifier. The voltage reference may also include slope, level and curvature trim circuits to provide a low-cost CMOS voltage reference that can be trimmed after final packaging. Due to the nulling of the errors from other sources by the nulling amplifier, the trim circuits are able to adjust the variations from the band-gap core. The nulling amplifier uses switching techniques to provide an accurate null, but is configured to avoid injecting switch transients into the voltage reference output.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: March 13, 2001
    Assignee: National Semiconductor Corporation
    Inventors: David R. MacQuigg, Mark J. Mercer
  • Patent number: 6198266
    Abstract: A low dropout voltage reference having three gain stages and two feedback loops, an overall loop and a secondary loop, is disclosed. The overall feedback loop establishes a desired output voltage. The secondary feedback loop provides two benefits: (1) a broadband reduction of the output impedance to ensure stability under various loading conditions and (2) an improvement in power supply rejection. The first benefit ensures that the pole created by the load capacitance and the output impedance of the amplifier doesn't adversely affect the overall loop stability. The second benefit helps improve line regulation. The low dropout voltage reference does not rely on a capacitor connected to the output to properly compensate the overall feedback loop. Therefore, the reference will work properly for a wide range of load capacitance values.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: March 6, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Mark J. Mercer
  • Patent number: 6166521
    Abstract: A control circuit is provided to minimize the charging cycle time of a battery charging system by maximizing the length of time that high constant charging current is applied to a discharged battery. The control circuit includes a constant current (CC) error amplifier, a constant voltage (CV) error amplifier, an output amplifier, and two pole-splitting compensation networks. The control circuit works in conjunction with a power source to charge a secondary battery. The pole-splitting compensation networks allow the CC, CV, and output amplifiers to be configured for high gain, without sacrificing output stability. The control circuit provides a sharp transition between the CC mode and CV mode of operation. In the CC mode, fast bulk battery charging is provided. In the CV mode, the control circuit initially provides a "top-off" charge to the battery and subsequently safely maintains the battery at its fully charged state.
    Type: Grant
    Filed: April 17, 2000
    Date of Patent: December 26, 2000
    Assignee: National Semiconductor Corporation
    Inventors: Mark J. Mercer, Stuart B. Shacter
  • Patent number: 6141193
    Abstract: A circuit (hereinafter "auto-shutoff regulator") for regulating the power provided to a load automatically opens and closes a switch (hereinafter "protection switch") to keep itself from being damaged by excessive power dissipation. The auto-shutoff regulator includes: (1) a shunt regulator coupled in parallel with the load and a power supply, and (2) another circuit (hereinafter "overpower detector") that monitors the power dissipated by the shunt regulator. The overpower detector has a control line (hereinafter "power shutoff line") that is coupled to the protection switch. When the power dissipated in the shunt regulator exceeds a predetermined threshold, the overpower detector drives a signal active on the power shutoff line, thereby to open the protection switch. Opening of the protection switch shuts off the supply of power to the shunt regulator, thereby to protect the shunt regulator from damage caused by excessive power dissipation.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: October 31, 2000
    Assignee: National Semiconductor Corporation
    Inventor: Mark J. Mercer
  • Patent number: 6100667
    Abstract: A control circuit is provided to minimize the charging cycle time of a battery charging system by maximizing the length of time that high constant charging current is applied to a discharged battery. The control circuit includes a constant current (CC) error amplifier, a constant voltage (CV) error amplifier, an output amplifier, and two pole-splitting compensation networks. The control circuit works in conjunction with a power source to charge a secondary battery. The pole-splitting compensation networks allow the CC, CV, and output amplifiers to be configured for high gain, without sacrificing output stability. The control circuit provides a sharp transition between the CC mode and CV mode of operation. In the CC mode, fast bulk battery charging is provided. In the CV mode, the control circuit initially provides a "top-off" charge to the battery and subsequently safely maintains the battery at its fully charged state.
    Type: Grant
    Filed: January 21, 1999
    Date of Patent: August 8, 2000
    Assignee: National Semiconductor Corporation
    Inventors: Mark J. Mercer, Stuart B. Shacter
  • Patent number: 5982148
    Abstract: A battery charger monitors the terminal voltage of a secondary battery connected thereto with no appreciable depletion of the battery energy. Upon the completion of the charge cycle, the battery charger monitors the terminal voltage of the battery by first creating a high impedance node at the battery low side, and then regulating the battery high side voltage to a value below the maximum allowable terminal voltage for the battery. The battery low side voltage will decreases in response to a value below ground. The charger monitors the terminal voltage across the battery by measuring the battery low side voltage When the battery charger detects that the battery has discharged to a predetermined capacity level, the charger initiates a charge maintenance mode. The battery charger either refreshes the battery or maintains the battery at the predetermined capacity level.
    Type: Grant
    Filed: June 22, 1998
    Date of Patent: November 9, 1999
    Assignee: National Semiconductor Corporation
    Inventor: Mark J. Mercer
  • Patent number: 4478546
    Abstract: A quick release bolt system utilizes two bolt sections. Each bolt section approximates one half of a bolt and has a half head portion and half threaded portion. Each section has an inner face which are parallel to and approach one another when the two bolt sections are assembled. A slide insert is receivable between the bolt section faces such that when the sections are assembled with the slide insert therebetween, the bolt can be threaded into a threaded receiving aperture in a block or the like with the threads of the bolt engaging the corresponding threads of the aperture. On the other hand, with the slide insert removed, the bolt sections approach each other and abut at their flat faces sufficiently close such that the two bolt sections can be slid into the threaded receiving aperture without the threads of the bolt sections engaging the threads of the threaded aperture.
    Type: Grant
    Filed: December 21, 1981
    Date of Patent: October 23, 1984
    Inventor: Mark J. Mercer