Patents by Inventor Mark J. Nietubyc

Mark J. Nietubyc has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6128321
    Abstract: A centrally-managed switch for interconnecting a plurality of digital signals through a plurality of selectable switch ports and controlled by a central management unit includes a cross-connect having a plurality of plesiochronous primary rate signal ports for receiving a plurality of plesiochronous primary rate signals, each plesiochronous primary rate signal comprising a plurality of channels, the cross-connect operable to switch ones of the channels of an originating plesiochronous primary rate signal to a destination plesiochronous primary rate signal.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: October 3, 2000
    Assignee: Alcatel USA Sourcing, L.P.
    Inventors: Shaun Bennett, Mark J. Nietubyc, Werner L. Heissenhuber, Michael H. Jette
  • Patent number: 5926480
    Abstract: An interface unit (12) for interfacing a digital loop carrier (16) to a digital cross-connect (14) comprises a control interface (22) coupled between the digital cross-connect (14) and digital loop carrier (16) for conversion and communication of control messages therebetween. A timing interface (32) is further coupled between the digital cross-connect (14) and digital loop carrier (16) for generally synchronizing the operations thereof. Further, a matrix interface (30) is coupled between the digital cross-connect (14) and digital loop carrier (16) for converting data rates and formats of data in the digital cross-connect (14) and digital loop carrier (16), so that network signals received by the digital loop carrier (16) are converted from a first format to a second format and communicated by the matrix interface (30) to the digital cross-connect (14) for cross-connection, and cross-connected data are converted from the second format to the first format and communicated to the digital loop carrier (16).
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: July 20, 1999
    Assignee: Alcatel USA Sourcing, L.P.
    Inventors: Stephen A. Deschaine, Clemente G. Garcia, Edward P. Traupman, Manouchehr Entezari, Mark J. Nietubyc, Werner L. Heissenhuber
  • Patent number: 5901024
    Abstract: Apparatus for redundancy circuit protection includes a controller (20), a plurality of circuits (22) coupled to the controller (20), and a redundancy switch (50) coupled between the plurality of circuits (22) and a network. The redundancy switch (50) is adapted for connecting or disconnecting selected ones of the plurality of circuits (22) to or from the network. In addition, a predetermined number of spare circuits (52) with similar functionality as the plurality of circuits (22) are coupled to the high density bank control unit (20), so that the redundancy switch (50) may connect or disconnect selected ones of the predetermined number of spare circuits (52) to the network and establish a transmission path from the controller (20) through the selected spare circuits (52) to the network.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: May 4, 1999
    Assignee: Alcatel USA Sourcing, L.P.
    Inventors: Stephen A. Deschaine, Mark J. Nietubyc, Werner L. Heissenhuber, Henry K. Lee, Mark W. Berry
  • Patent number: 5886994
    Abstract: Apparatus and method are provided which map E1 signals into a logical space of a predetermined number of DS1 signals. 24 selected DS0 signals that are part of each E1 signal are mapped into the space of one DS1 signal in the logical space. The remaining eight DS0 signals of every three E1 signal are then interleavingly mapped into the space of one DS1 signal in the logical space. Depending on the defined logical space, additional E1 signals are mapped into the logical space in the same manner until the predetermined number of DS1 signal spaces in the defined logical space are filled.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: March 23, 1999
    Assignee: Alcatel USA Sourcing, L.P.
    Inventors: Stephen A. Deschaine, Manouchehr Entezari, Mark J. Nietubyc, Werner L. Heissenhuber
  • Patent number: 5883898
    Abstract: Apparatus and method are provided which map E1 signals into a logical space of a predetermined number of DS1 signals. 24 selected DS0 signals that are part of the first E1 signal are mapped into the space of a first DS1 signal in the logical space. The 8 DS0 signals of the first E1 signal are then mapped into the space of a second DS1 signal in the logical space. Depending on the defined logical space, additional E1 signals may be mapped into the logical space of two DS1 signals in the same manner until the predetermined number of DS1 signal spaces in the defined logical space are filled.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: March 16, 1999
    Assignee: Alcatel USA Sourcing, L.P.
    Inventors: Stephen A. Deschaine, Manouchehr Entezari, Mark J. Nietubyc, Werner L. Heissenhuber