Patents by Inventor Mark J. Palmer

Mark J. Palmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7020958
    Abstract: Methods of assembling an electronic package including forming a housing with a first bond pad on a top surface of a bond shelf, forming a conductive strip along a side surface or edge of the bond shelf, and removing a portion of the conductive strip to form a pair of separate conductive strips. The conductive strip may be formed by plating a conductive material onto the bond shelf into unmasked areas thereof. The conductive strip may include a portion that extends around from the side surface to the top surface of the bond shelf to form a bond pad or couple to a bond pad on the top surface. The extended portion may also anchor the conductive strip and the separate conductive strips to the housing and reduce the likelihood of delamination during removal of the portion of the conductive strip to form the separate conductive strips.
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: April 4, 2006
    Assignee: Intel Corporation
    Inventors: Elissa E. Carapella, Mark J. Palmer
  • Publication number: 20040046243
    Abstract: An electronic package that may include a first bond pad and a second bond pad located on a bond shelf. The bond shelf may have an edge. The package may have a first conductive bus that may be connected to the first bond pad by a first conductive strip that extends along the edge of the bond shelf. The package may also have a second conductive bus that may be connected to the second bond pad by a second conductive strip that extends along the edge of the bond shelf.
    Type: Application
    Filed: September 8, 2003
    Publication date: March 11, 2004
    Inventors: Elissa E. Carapella, Mark J. Palmer
  • Patent number: 6153829
    Abstract: An electronic package that may include a first bond pad and a second bond pad located on a bond shelf. The bond shelf may have an edge. The package may have a first conductive bus that may be connected to the first bond pad by a first conductive strip that extends along the edge of the bond shelf. The package may also have a second conductive bus that may be connected to the second bond pad by a second conductive strip that extends along the edge of the bond shelf.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: November 28, 2000
    Assignee: Intel Corporation
    Inventors: Elissa E. Carapella, Mark J. Palmer
  • Patent number: 6008988
    Abstract: A multi-chip module which contains a heat spreader that maintains a relatively uniform temperature profile between the devices of the module. The module includes a first electronic device and a second electronic device that are both mounted to a package. The devices are electrically connected by routing within the package. A heat spreader that is thermally coupled to both devices. The heat spreader transfers the heat generated by the electronic devices so that the devices operate at approximately the same temperature. A heat slug may be attached to the heat spreader to reduce the thermal impedance of the module.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: December 28, 1999
    Assignee: Intel Corporation
    Inventor: Mark J. Palmer
  • Patent number: 5721454
    Abstract: An integrated circuit package which has vias that provide the dual function of electrically grounding an integrated circuit and removing heat generated by the circuit. The package has a bonding shelf extending from a base portion. The bonding shelf has a plurality of bonding pads that are connected to corresponding pads on a top surface of the integrated circuit. The integrated circuit is mounted to the base portion of the package. The base portion has a plurality of surface pads that are connected to corresponding ground pads on the integrated circuit. Located between the base portion and an external bottom surface of the package is a ground bus. The package has a plurality of vias that electrically connect the surface pads and integrated circuit to the ground bus. The vias further extend to the external bottom surface to provide a thermal path between the integrated circuit and the outside of the package.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: February 24, 1998
    Assignee: Intel Corporation
    Inventor: Mark J. Palmer
  • Patent number: 5691569
    Abstract: A contact pattern for an integrated circuit package. The package has a plurality of contacts that are soldered to corresponding pads of a printed circuit board. The contacts are arranged into a plurality of cell units. Each cell unit has a row of center contacts diagonally located between two rows of outer contacts. The diagonally located pins increase the density of the contact pattern. Each unit cell is separated by a space that allows routing traces to be routed therethrough. Routing traces may also be routed through the unit cells to increase the routing density of the package. The package provides a contact pattern that optimizes both the pin density and the routing traces.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: November 25, 1997
    Assignee: Intel Corporation
    Inventor: Mark J. Palmer
  • Patent number: 5483099
    Abstract: An integrated circuit package that is coupled to a printed circuit board by a socket assembly. The socket assembly has a plurality of pins that are mounted to the circuit board. The pins are coupled to corresponding conductive sockets and outer rings of the socket assembly. The package contains an integrated circuit that is coupled to external pins which extend from a bottom surface of the package housing. The package also has a plurality of conductive rings that are located on the bottom surface of the housing and are electrically coupled to the integrated circuit. To install the package, the package pins are inserted into the individual sockets of the socket assembly. Insertion of the pins also presses the conductive rings of the package onto the corresponding outer rings of the socket. The conductive rings are typically dedicated to the power and ground pins of the system, wherein the integrated circuit receives power through the rings.
    Type: Grant
    Filed: August 31, 1994
    Date of Patent: January 9, 1996
    Assignee: Intel Corporation
    Inventors: Siva Natarajan, Udy Shrivastava, William M. Siu, Mark J. Palmer