Abstract: An apparatus for controlling light emission and/or sensing in an array of optical elements. An infra-extensible array having a plurality of subarray display circuits interconnected with neighboring subarray display circuits. Each subarray display circuit is configured with a processor and a plurality of output and/or input elements. Messages and instructions can be propagated from one subarray display circuit to another to provide local processing relating to input and output elements, such as changing the pixels in the display from a subarray display circuit in response to locally sensed conditions or those communicated from neighboring subarray display circuits. Apparatus is infra-extensible as both the number of processors for executing display/sensor programming, and the number of communication channels available through which instructions can be received, increases automatically in response to increasing the number of subarray display circuits within the apparatus.

Abstract: An apparatus and method controlling cellular automata containing a plurality of cascaded circuit cells having logic units. The cells are interleaved in groups toward supporting multiple directions, for example quad cells in which each cells of the quad is directed in a different directions separated by a fixed angle, such as 90 degrees (i.e., north, east, south, and west). These cells are triggered asynchronously as each cell is stabilized in preparation for receiving the trigger. The cells process data selectively based on the configuration of the cell and in response to receipt of data and trigger (or combined data and trigger) conditions from neighboring cells. The array can be utilized within a wide range of digital logic. As there is no need for distributing a global clock across the array of cells, the size of the array can be extended to any desired dimension.

Abstract: An apparatus and method controlling cellular automata containing a plurality of cascaded circuit cells having logic units. The cells are interleaved in groups toward supporting multiple directions, for example quad cells in which each cells of the quad is directed in a different directions separated by a fixed angle, such as 90 degrees (i.e., north, east, south, and west). These cells are triggered asynchronously as each cell is stabilized in preparation for receiving the trigger. The cells process data selectively based on the configuration of the cell and in response to receipt of data and trigger (or combined data and trigger) conditions from neighboring cells. The array can be utilized within a wide range of digital logic. As there is no need for distributing a global clock across the array of cells, the size of the array can be extended to any desired dimension.

Abstract: Apparatus and methods are provided for rapid and sensitive quantitative analysis of a sample's fluorescence decay properties. A repetitively pulsed excitation light source generates pulsed fluorescence in the sample. A fluorescence wavelength selector receives a portion of the pulsed fluorescence emanating from the sample and outputs fluorescence photons whose wavelengths lie within a specified wavelength range. A photodetector receives the fluorescence photons within the specified wavelength range as an input from the fluorescence wavelength selector and outputs a time-dependent electrical signal. An array of memory elements stores a representation of the time-dependent electrical signal as a time-series of analog voltages or charges. Successive elements in the array correspond to a time increment of no greater than 4 ns. An analog-to-digital converter transforms the time-series of analog voltages or charges into a corresponding digitized fluorescence waveform.

Abstract: An apparatus for capturing and digitizing a signal derived from an event has a memory for storing a sequence of analog samples from the signal derived from the event in a sampling operation occurring at about a 0.5 gigahertz or higher sampling rate. Circuitry communicating with the memory selectively initiates the read out of the analog samples in the memories. An array of analog to digital converters receives a sequence of analog samples read out from the memory and produces from the analog samples a corresponding vector of digitized sample values. A waveform accumulator integrated with the array of analog to digital converters receives a vector of digitized sample values from a new waveform and combines these with a vector of digitized sample values from at least one prior waveform. An output stage outputs the vector of digitized sample values developed in the waveform accumulator.

Abstract: An apparatus for capturing and digitizing at least one analog signal derived from an event with a signal duration that is short compared to the interval between consecutive analog signals has two or more memories each capable of storing a sequence of analog samples of one of two or more analog signals derived from the event. There is a trigger for triggering the sampling and storage in the two or more memories of a sequence of analog samples to occur at about a 0.5 gigahertz or higher rate and circuitry communicating with the memories for selectively initiating the read out of the analog samples in the memories. An analog to digital converter receives each analog sample read out from each of memories and produces from the analog samples corresponding digitized sample values.

Abstract: An apparatus for capturing and digitizing at least one analog signal derived from an event with a signal duration that is short compared to the interval between consecutive analog signals has two or more memories each capable of storing a sequence of analog samples of one of two or more analog signals derived from the event. There is a trigger for triggering the sampling and storage in the two or more memories of a sequence of analog samples to occur at about a 0.5 gigahertz or higher rate and circuitry communicating with the memories for selectively initiating the read out of the analog samples in the memories. An analog to digital converter receives each analog sample read out from each of memories and produces from the analog samples corresponding digitized sample values.

Abstract: Apparatus and methods are provided for rapid and sensitive quantitative analysis of a sample's fluorescence decay properties. A repetitively pulsed excitation light source generates pulsed fluorescence in the sample. A fluorescence wavelength selector receives a portion of the pulsed fluorescence emanating from the sample and outputs fluorescence photons whose wavelengths lie within a specified wavelength range. A photodetector receives the fluorescence photons within the specified wavelength range as an input from the fluorescence wavelength selector and outputs a time-dependent electrical signal. An array of memory elements stores a representation of the time-dependent electrical signal as a time-series of analog voltages or charges. Successive elements in the array correspond to a time increment of no greater than 4 ns. An analog-to-digital converter transforms the time-series of analog voltages or charges into a corresponding digitized fluorescence waveform.

Abstract: SIMD computer architecture is used in conjunction with a host processor and coordinate processor to render quality, three-dimensional, anti-aliased shaded color images into the frame buffer of a video display system. The method includes a parallel algorithm for rendering an important graphic primitive for accomplishing the production of a smoothly shaded color three-dimensional triangle with anti-aliased edges. By taking advantage of the SIMD architecture and said parallel algorithm, the very time consuming pixel by pixel computations are broken down for parallel execution. A single coordinate processor computes and transmits an overall triangle record which is essentially the same for all blocks of pixels within a given bounding box which box in turn surrounds each triangle. The individual pixel data is produced by a group of M.times.N pixel processors and stored in the frame buffer in a series of repetitive steps wherein each step corresponds to the processing of an M.times.

Abstract: Attribute hierarchy system including hardware assisted by software for utilizing a stack structure of a multiple-level stack and a plurality of stacks for storing data and attributes. The stack structure provides that only the top of the stack is loaded and utilized. The software controls the hardware logic flow associated with the stack and the stacks. The hardware includes an attribute memory and character data storage, a character data counter and position register. An attribute mask and attribute processor control loading of the attributes. A command register pushes, pops or loads to the stacks along with a sequence controller input from the attribute processor. A command decoder determines sequence of operation for loading attributes and character into row buffers. A stack control flags when a valid load has occurred, and if no load occurred, the stack defaults and a copy operation occurs.

Abstract: An intelligent programmable process control system including a first microprocessor which scans and executes a sequence of boolean logic functions and a second microprocessor which performs complex operations including arithmetic computations beyond the capabilities of the first microprocessor. The first microprocessor transmits interrupt requests to the second microprocessor when a scanned sequence instruction requires complex operations to be performed. First flag bit register indicates to the first microprocessor that a requested operation has been queued-up. Second flag bit register indicates to the first microprocessor that the requested operation has been completed.