Patents by Inventor Mark J. Pouliot

Mark J. Pouliot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Enhanced efficiency solar cells and method of manufacture
    Patent number: 8217259
    Abstract: Enhanced efficiency solar cells and methods of manufacture of such cells are described herein. In an illustrative example, the solar cell includes at least one or more collector lens bars each of which extend on sides of front contacts and positioned over a respective active area of one or more active areas in such as position as to guide light onto the one or more active areas. A protective layer covers the at least one or more collector lens bars.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: July 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Scott W. Jones, Robert K. Leidy, Mark J. Pouliot
  • ENHANCED EFFICIENCY SOLAR CELLS AND METHOD OF MANUFACTURE
    Publication number: 20100175750
    Abstract: Enhanced efficiency solar cells and methods of manufacture of such cells are described herein. In an illustrative example, the solar cell includes at least one or more collector lens bars each of which extend on sides of front contacts and positioned over a respective active area of one or more active areas in such as position as to guide light onto the one or more active areas. A protective layer covers the at least one or more collector lens bars.
    Type: Application
    Filed: May 29, 2009
    Publication date: July 15, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Scott W. Jones, Robert K. Leidy, Mark J. Pouliot
  • Crack stop for low K dielectrics
    Patent number: 7521336
    Abstract: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: April 21, 2009
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Stephen E. Luce, Thomas L. McDevitt, William T. Motsiff, Mark J. Pouliot, Jennifer C. Robbins
  • Crack stop for low K dielectrics
    Patent number: 7335577
    Abstract: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: February 26, 2008
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Stephen E. Luce, Thomas L. McDevitt, William T. Motsiff, Mark J. Pouliot, Jennifer C. Robbins