Patents by Inventor Mark J. Saly
Mark J. Saly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240360549Abstract: A method includes performing a reactant step of a deposition cycle of a deposition process to form a molybdenum (Mo)-based material, performing a Mo precursor step of the deposition cycle, and performing a treatment step of the deposition cycle. Performing the reactant step includes introducing a reactant, performing the Mo precursor step includes introducing a Mo precursor, and performing the treatment step includes introducing a treatment gas. The deposition process is performed at a temperature that is less than or equal to about 450° C.Type: ApplicationFiled: April 27, 2023Publication date: October 31, 2024Inventors: Feng Q. Liu, Byunghoon Yoon, Joung-Joo Lee, Avgerinos V. Gelatos, Mark J. Saly
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Publication number: 20240332001Abstract: Exemplary methods of semiconductor processing may include providing a first precursor to a semiconductor processing chamber. A substrate may be disposed within a processing region of the semiconductor processing chamber. The substrate may define a feature. The methods may include contacting the substrate with the first precursor. The contacting may form a first portion of a silicon-carbon-and-nitrogen-containing material on the substrate. The methods may include providing a second precursor to the semiconductor processing chamber. The methods may include contacting the substrate with the second precursor. The contacting may form the silicon-carbon-and-nitrogen-containing material on the substrate. The silicon-carbon-and-nitrogen-containing material may be void free.Type: ApplicationFiled: March 30, 2023Publication date: October 3, 2024Applicant: Applied Materials, Inc.Inventors: Lakmal C. Kalutarage, Bhaskar Jyoti Bhuyan, Mark J. Saly, Jeffrey W. Anthis
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Publication number: 20240282632Abstract: A method includes selectively forming at least one passivation layer on at least one first conductive layer disposed in a first interlevel dielectric (ILD) layer, selectively forming at least one catalyst layer on the at least one passivation layer, wherein the at least one passivation layer prevents formation of the at least one catalyst layer on the first conductive layer, and selectively forming at least one supplemental dielectric layer using the at least one catalyst layer. The at least one catalyst layer induces formation of the at least one supplemental dielectric layer, and the at least one supplemental dielectric layer includes a dielectric material having a dielectric constant of less than or equal to about 4.Type: ApplicationFiled: February 14, 2023Publication date: August 22, 2024Inventors: Zachary J. Devereaux, Bhaskar Jyoti Bhuyan, Thomas Joseph Knisley, Zeqing Shen, Susmit Singha Roy, Mark J. Saly, Abhijit Basu Mallick
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Publication number: 20240266180Abstract: A method includes performing a dry etch process to remove a portion of a first layer disposed on a second layer of a stack of alternating layers. The first layer includes a first material and the second layer includes a second material different from the first material, and the dry etch process forms a passivation layer including a byproduct on surfaces of the second material. A amount of first material of the portion of the first layer remains after performing the dry etch process, The method further includes introducing a halide gas to enhance the passivation layer on the surfaces of the second material.Type: ApplicationFiled: February 1, 2024Publication date: August 8, 2024Inventors: David Knapp, Feng Qiao, Hailong Zhou, Junkai He, Qian Fu, Mark J. Saly, Jeffrey Anthis, Jayoung Choi
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Patent number: 12014925Abstract: Exemplary deposition methods may include delivering a ruthenium-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. At least one of the ruthenium-containing precursor or the hydrogen-containing precursor may include carbon. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a ruthenium-and-carbon material on a substrate disposed within the processing region of the semiconductor processing chamber.Type: GrantFiled: May 25, 2021Date of Patent: June 18, 2024Assignee: Applied Materials, Inc.Inventors: Eswaranand Venkatasubramanian, Bhaskar Jyoti Bhuyan, Mark J. Saly, Abhijit Basu Mallick
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Publication number: 20240145232Abstract: A method includes forming a first layer and a second layer on a substrate, forming a passivation layer on a surface of the first layer without forming the passivation layer on a surface of the second layer by exposing the first layer and the second layer to a benzyl compound, and after forming the passivation layer on the first layer, performing at least one of: depositing a third layer on the second layer, or etching the second layer.Type: ApplicationFiled: October 28, 2022Publication date: May 2, 2024Inventors: Feng Q. Liu, Mark J. Saly, David Thompson
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Publication number: 20240128091Abstract: A method includes providing, within an etch chamber, a base structure including a target layer disposed on a substrate, and an etch mask disposed on the target layer, dry etching, within the etch chamber, the target layer using thionyl chloride to obtain a processed base structure, and after forming the plurality of features. The processed base structure includes a plurality of features and a plurality of openings defined by the etch mask. The method further includes removing the processed base structure from the etch chamber. In some embodiments, the target layer includes carbon. In some embodiments, the dry etching is performed at a sub-zero degree temperature.Type: ApplicationFiled: July 12, 2023Publication date: April 18, 2024Inventors: Zhonghua Yao, Qian Fu, Mark J. Saly, Yang Yang, Jeffrey W. Anthis, David Knapp, Rajesh Sathiyanarayanan
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Patent number: 11942330Abstract: Exemplary methods of etching gallium oxide from a semiconductor substrate may include flowing a first reagent in a substrate processing region housing the semiconductor substrate. The first reagent may include HX. X may be at least one of fluorine, chlorine, and bromine. The semiconductor substrate may include an exposed region of gallium oxide. Fluorinating the exposed region of gallium oxide may form a gallium halide and H2O. The methods may include flowing a second reagent in the substrate processing region. The second reagent may be at least one of trimethylgallium, tin acetylacetonate, tetramethylsilane, and trimethyltin chloride. The second reagent may promote a ligand exchange where a methyl group may be transferred to the gallium halide to form a volatile Me2GaY or Me3Ga. Y may be at least one of fluorine, chlorine, and bromine from the second reagent. The methods may include recessing a surface of the gallium oxide.Type: GrantFiled: June 9, 2022Date of Patent: March 26, 2024Assignee: Applied Materials, Inc.Inventors: Feng Q. Liu, Lisa J. Enman, Lakmal C. Kalutarage, Mark J. Saly
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Patent number: 11932938Abstract: Disclosed is a coated chamber component comprising a body having a reduced metal surface such that the reduced metal surface has less metal oxide as compared to an amount of metal oxide on a metal surface that has not been reduced. The metal surface may be reduced by pulsing a reducing alcohol thereon. The reduced metal surface may be coated with a corrosion resistant film that may be deposited onto the reduced metal surface by a dry atomic layer deposition process.Type: GrantFiled: July 22, 2020Date of Patent: March 19, 2024Assignee: Applied Materials, Inc.Inventors: Lisa J. Enman, Steven D. Marcus, Mark J. Saly, Lei Zhou
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Publication number: 20240003003Abstract: Disclosed is a coated chamber component comprising a body having a reduced metal surface such that the reduced metal surface has less metal oxide as compared to an amount of metal oxide on a metal surface that has not been reduced. The metal surface may be reduced by pulsing a reducing alcohol thereon. The reduced metal surface may be coated with a corrosion resistant film that may be deposited onto the reduced metal surface by a dry atomic layer deposition process.Type: ApplicationFiled: September 14, 2023Publication date: January 4, 2024Inventors: Lisa J. Enman, Steven D. Marcus, Mark J. Saly, Lei Zhou
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Publication number: 20230243068Abstract: Embodiments generally relate to methods for depositing silicon-phosphorous materials, and more specifically, relate to using silicon-phosphorous compounds in vapor deposition processes (e.g., epitaxy, CVD, or ALD) to deposit silicon-phosphorous materials. In one or more embodiments, a method for forming a silicon-phosphorous material on a substrate is provided and includes exposing the substrate to a deposition gas containing one or more silicon-phosphorous compounds during a deposition process and depositing a film containing the silicon-phosphorous material on the substrate. The silicon-phosphorous compound has the chemical formula [(R3-vHvSi)—(R2-wHwSi)n]xPHyR?z, where each instance of R and each instance of R? are independently an alkyl or a halogen, n is 0, 1, or 2; v is 0, 1, 2, or 3; w is 0, 1, or 2; x is 1, 2, or 3; y is 0, 1, or 2; z is 0, 1, or 2, and where x+y+z=3.Type: ApplicationFiled: April 5, 2023Publication date: August 3, 2023Inventors: Errol Antonio C. SANCHEZ, Mark J. SALY, Schubert CHU, Abhishek DUBE, Srividya NATARAJAN
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Patent number: 11649560Abstract: Embodiments generally relate to methods for depositing silicon-phosphorous materials, and more specifically, relate to using silicon-phosphorous compounds in vapor deposition processes (e.g., epitaxy, CVD, or ALD) to deposit silicon-phosphorous materials. In one or more embodiments, a method for forming a silicon-phosphorous material on a substrate is provided and includes exposing the substrate to a deposition gas containing one or more silicon-phosphorous compounds during a deposition process and depositing a film containing the silicon-phosphorous material on the substrate. The silicon-phosphorous compound has the chemical formula [(R3-vHvSi)—(R2-wHwSi)n]xPHyR?z, where each instance of R and each instance of R? are independently an alkyl or a halogen, n is 0, 1, or 2; v is 0, 1, 2, or 3; w is 0, 1, or 2; x is 1, 2, or 3; y is 0, 1, or 2; z is 0, 1, or 2, and where x+y+z=3.Type: GrantFiled: August 2, 2019Date of Patent: May 16, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Errol Antonio C Sanchez, Mark J. Saly, Schubert Chu, Abhishek Dube, Srividya Natarajan
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Publication number: 20230002878Abstract: Disclosed herein is a method for forming metal-oxides in the photoresist to improve profile control. The method includes infiltrating a metal oxide in a photoresist layer by pressurizing a methyl-containing material in a processing environment proximate a film stack. The film stack includes the photoresist layer, the photoresist layer being disposed on top of and in contact with an underlayer. The underlayer disposed on top of a substrate. The method includes etching the film stack including the photoresist layer implanted with the metal oxide.Type: ApplicationFiled: May 10, 2022Publication date: January 5, 2023Inventors: Nancy FUNG, Mark J. SALY
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Patent number: 11536708Abstract: Embodiments of the present disclosure provide dual pore sensors and methods for producing these dual pore sensors. The method includes forming a film stack, where the film stack contains two silicon layers and two membrane layers, and then etching the film stack to produce a channel extending therethrough and having two reservoirs and two nanopores. The method also includes depositing a oxide layer on inner surfaces of the reservoirs and nanopores, depositing a dielectric layer on the oxide layer, and forming a metal contact extending through a portion of the stack. The method further includes etching the dielectric layers to form wells, etching the first silicon layer to reveal the protective oxide layer deposited on the inner surfaces of a reservoir, and etching the protective oxide layer deposited on the inner surfaces of the reservoirs and the nanopores.Type: GrantFiled: January 9, 2020Date of Patent: December 27, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Mark J. Saly, Keenan Navarre Woods, Joseph R. Johnson, Bhaskar Jyoti Bhuyan, William J. Durand, Michael Chudzik, Raghav Sreenivasan, Roger Quon
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Publication number: 20220384188Abstract: Exemplary deposition methods may include delivering a ruthenium-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. At least one of the ruthenium-containing precursor or the hydrogen-containing precursor may include carbon. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a ruthenium-and-carbon material on a substrate disposed within the processing region of the semiconductor processing chamber.Type: ApplicationFiled: May 25, 2021Publication date: December 1, 2022Applicant: Applied Materials, Inc.Inventors: Eswaranand Venkatasubramanian, Bhaskar Jyoti Bhuyan, Mark J. Saly, Abhijit Basu Mallick
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Publication number: 20220301883Abstract: Exemplary methods of etching gallium oxide from a semiconductor substrate may include flowing a first reagent in a substrate processing region housing the semiconductor substrate. The first reagent may include HX. X may be at least one of fluorine, chlorine, and bromine. The semiconductor substrate may include an exposed region of gallium oxide. Fluorinating the exposed region of gallium oxide may form a gallium halide and H2O. The methods may include flowing a second reagent in the substrate processing region. The second reagent may be at least one of trimethylgallium, tin acetylacetonate, tetramethylsilane, and trimethyltin chloride. The second reagent may promote a ligand exchange where a methyl group may be transferred to the gallium halide to form a volatile Me2GaY or Me3Ga. Y may be at least one of fluorine, chlorine, and bromine from the second reagent. The methods may include recessing a surface of the gallium oxide.Type: ApplicationFiled: June 9, 2022Publication date: September 22, 2022Applicant: Applied Materials, Inc.Inventors: Feng Q. Liu, Lisa J. Enman, Lakmal C. Kalutarage, Mark J. Saly
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Patent number: 11398388Abstract: Exemplary methods of etching gallium oxide from a semiconductor substrate may include selectively etching gallium oxide relative to gallium nitride. The method may include flowing a reagent in a substrate processing region housing the semiconductor substrate. The reagent may include at least one of chloride and bromide. The method may further include contacting an exposed region of gallium oxide with the at least one of chloride and bromide from the reagent to form a gallium-containing gas. The gallium-containing gas may be removed by purging the substrate processing region with an inert gas. The method includes recessing a surface of the gallium oxide. The method may include repeated cycles to achieve a desired depth.Type: GrantFiled: September 8, 2020Date of Patent: July 26, 2022Assignee: Applied Materials, Inc.Inventors: Feng Q. Liu, Lisa J. Enman, Lakmal C. Kalutarage, Mark J. Saly
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Publication number: 20220076960Abstract: Exemplary methods of etching gallium oxide from a semiconductor substrate may include selectively etching gallium oxide relative to gallium nitride. The method may include flowing a reagent in a substrate processing region housing the semiconductor substrate. The reagent may include at least one of chloride and bromide. The method may further include contacting an exposed region of gallium oxide with the at least one of chloride and bromide from the reagent to form a gallium-containing gas. The gallium-containing gas may be removed by purging the substrate processing region with an inert gas. The method includes recessing a surface of the gallium oxide. The method may include repeated cycles to achieve a desired depth.Type: ApplicationFiled: September 8, 2020Publication date: March 10, 2022Applicant: Applied Materials, Inc.Inventors: Feng Q. Liu, Lisa J. Enman, Lakmal C. Kalutarage, Mark J. Saly
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Patent number: 11107674Abstract: Embodiments described and discussed herein provide methods for depositing silicon nitride materials by vapor deposition, such as by flowable chemical vapor deposition (FCVD), as well as for utilizing new silicon-nitrogen precursors for such deposition processes. The silicon nitride materials are deposited on substrates for gap fill applications, such as filling trenches formed in the substrate surfaces. In one or more embodiments, the method for depositing a silicon nitride film includes introducing one or more silicon-nitrogen precursors and one or more plasma-activated co-reactants into a processing chamber, producing a plasma within the processing chamber, and reacting the silicon-nitrogen precursor and the plasma-activated co-reactant in the plasma to produce a flowable silicon nitride material on a substrate within the processing chamber. The method also includes treating the flowable silicon nitride material to produce a solid silicon nitride material on the substrate.Type: GrantFiled: November 11, 2019Date of Patent: August 31, 2021Assignee: Applied Materials, Inc.Inventors: Lakmal C. Kalutarage, Mark J. Saly, Praket Prakash Jha, Jingmei Liang
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Publication number: 20210215664Abstract: Embodiments of the present disclosure provide dual pore sensors and methods for producing these dual pore sensors. The method includes forming a film stack, where the film stack contains two silicon layers and two membrane layers, and then etching the film stack to produce a channel extending therethrough and having two reservoirs and two nanopores. The method also includes depositing a oxide layer on inner surfaces of the reservoirs and nanopores, depositing a dielectric layer on the oxide layer, and forming a metal contact extending through a portion of the stack. The method further includes etching the dielectric layers to form wells, etching the first silicon layer to reveal the protective oxide layer deposited on the inner surfaces of a reservoir, and etching the protective oxide layer deposited on the inner surfaces of the reservoirs and the nanopores.Type: ApplicationFiled: January 9, 2020Publication date: July 15, 2021Inventors: Mark J. SALY, Keenan Navarre WOODS, Joseph R. JOHNSON, Bhaskar Jyoti BHUYAN, William J. DURAND, Michael CHUDZIK, Raghav SREENIVASAN, Roger QUON