Patents by Inventor Mark Jaffe

Mark Jaffe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7528427
    Abstract: A pixel sensor cell structure and method of manufacture. Disclosed is a pixel sensor cell comprising an asymmetric transfer gate for providing a pinning layer having an edge spaced a further distance from the gate channel region than an edge of a charge collection well. Potential barrier interference to charge transfer caused by the pinning layer is reduced.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: May 5, 2009
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Gambino, Mark Jaffe
  • Publication number: 20080179639
    Abstract: A pixel sensor cell structure and method of manufacture. Disclosed is a pixel sensor cell comprising an asymmetric transfer gate for providing a pinning layer having an edge spaced a further distance from the gate channel region than an edge of a charge collection well. Potential barrier interference to charge transfer caused by the pinning layer is reduced.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Inventors: Jeffrey Gambino, Mark Jaffe
  • Publication number: 20080108170
    Abstract: A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.
    Type: Application
    Filed: December 19, 2007
    Publication date: May 8, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Adkisson, Jeffrey Gambino, Mark Jaffe, Robert Leidy, Richard Rassel, Anthony Stamper
  • Publication number: 20080073742
    Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.
    Type: Application
    Filed: November 20, 2007
    Publication date: March 27, 2008
    Inventors: James Adkisson, Jeffrey Gambino, Mark Jaffe, Robert Leidy, Stephen Luce, Richard Rassell, Edmund Sprogis
  • Publication number: 20070296006
    Abstract: The present invention relates to a design structure for a pixel sensor cell. The pixel sensor cell approximately doubles the available signal for a given quanta of light. A design structure for a pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.
    Type: Application
    Filed: September 6, 2007
    Publication date: December 27, 2007
    Inventors: James Adkisson, Andres Bryant, John Ellis-Monaghan, Mark Jaffe, Jeffrey Johnson, Alain Loiseau
  • Publication number: 20070267698
    Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.
    Type: Application
    Filed: July 9, 2007
    Publication date: November 22, 2007
    Inventors: Kerry Bernstein, Timothy Dalton, Jeffrey Gambino, Mark Jaffe, Paul Kartschoke, Anthony Stamper
  • Publication number: 20070235780
    Abstract: An imaging circuit, an imaging sensor, and a method of imaging. The imaging cell circuit including one or more imaging cell circuits, each imaging cell circuit comprising: a transistor having a floating body for holding charge generated in the floating body in response to exposure of the floating body to electromagnetic radiation; means for biasing the transistor wherein an output of the transistor is responsive to the electromagnetic radiation; and means for selectively connecting the floating body to a reset voltage supply.
    Type: Application
    Filed: June 20, 2007
    Publication date: October 11, 2007
    Inventors: John Ellis-Monaghan, Mark Jaffe, Alain Loiseau
  • Publication number: 20070202635
    Abstract: The present invention relates to semiconductor-on-insulator (SOI) substrate structures that contain surface semiconductor regions of different crystal orientations located directly on an insulator layer. The present invention also relates to methods for fabricating such SOI substrate structures, by growing an insulator layer directly on a multi-orientation bulk semiconductor substrate that comprises surface semiconductor regions of different crystal orientations located directly on a semiconductor base layer, and removing the semiconductor base layer, thereby forming a multi-orientation SOI substrate structure that comprises surface semiconductor regions of different crystal orientations located directly on the insulator layer.
    Type: Application
    Filed: February 27, 2006
    Publication date: August 30, 2007
    Inventors: John Ellis-Monaghan, Mark Jaffe
  • Publication number: 20070194397
    Abstract: An imaging sensor with an array of FET pixels and method of forming the imaging sensor. Each pixel is a semiconductor island, e.g., N-type silicon on a Silicon on insulator (SOI) wafer. FETs are formed in one photodiode electrode, e.g., a P-well cathode. A color filter may be attached to an opposite surface of island. A protective layer (e.g., glass or quartz) or window is fixed to the pixel array at the color filters. The image sensor may be illuminated from the backside with cell wiring above the cell. So, an optical signal passes through the protective layer is filtered by the color filters and selectively sensed by a corresponding photo-sensor.
    Type: Application
    Filed: February 17, 2006
    Publication date: August 23, 2007
    Inventors: James Adkisson, Jeffrey Gambino, Mark Jaffe, Alan Loiseau, Richard Rassel
  • Publication number: 20070187734
    Abstract: A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface.
    Type: Application
    Filed: February 14, 2006
    Publication date: August 16, 2007
    Inventors: James Adkisson, John Ellis-Monaghan, Mark Jaffe, Dale Pearson, Dennis Rogers
  • Publication number: 20070187787
    Abstract: A pixel for an image sensor includes a photosensor located within a substrate. A patterned dielectric layer having an aperture registered with the photosensor is located over the substrate. A lens structure is located over the dielectric layer and also registered with the photosensor. A liner layer is located contiguously upon a top surface of the dielectric layer, and the sidewalls and bottom of the aperture. The liner layer provides for enhanced reflection for off-axis incoming light and enhanced capture thereof by the photosensor. When the aperture does not provide a dielectric layer border for a metallization layer embedded within the dielectric layer, an exposed edge of the metallization layer may be chamfered.
    Type: Application
    Filed: February 16, 2006
    Publication date: August 16, 2007
    Inventors: Kristin Ackerson, James Adkisson, John Ellis-Monaghan, Jeffrey Gambino, Timothy Hoague, Mark Jaffe, Robert Leidy, Matthew Moon, Richard Passel
  • Publication number: 20070184614
    Abstract: A novel CMOS image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate having an upper surface, a gate comprising a dielectric layer formed on the substrate and a gate conductor formed on the gate dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. A portion of the bottom of the gate conductor is recessed below the surface of the substrate.
    Type: Application
    Filed: April 13, 2007
    Publication date: August 9, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Adkisson, John Ellis-Monaghan, Mark Jaffe, Jerome Lasky
  • Publication number: 20070158711
    Abstract: Structures and method for forming the same. The semiconductor structure comprises a photo diode that includes a first semiconductor region and a second semiconductor region. The first and second semiconductor regions are doped with a first and second doping polarities, respectively, and the first and second doping polarities are opposite. The semiconductor structure also comprises a transfer gate that comprises (i) a first extension region, (ii) a second extension region, and (iii) a floating diffusion region. The first and second extension regions are in direct physical contact with the photo diode and the floating diffusion region, respectively. The semiconductor structure further comprises a charge pushing region. The charge pushing region overlaps the first semiconductor region and does not overlap the floating diffusion region. The charge pushing region comprises a transparent and electrically conducting material.
    Type: Application
    Filed: January 10, 2006
    Publication date: July 12, 2007
    Inventors: James Adkisson, Jeffrey Gambino, Mark Jaffe, Jeffrey Johnson, Jerome Lasky, Richard Rassel
  • Publication number: 20070153104
    Abstract: A pixel array in an image sensor, the image sensor and a digital camera including the image sensor. The image sensor includes a pixel array with colored pixels and unfiltered (color filter-free) pixels. Each unfiltered pixel occupies one or more array locations. The colored pixels may be arranged in uninterrupted rows and columns with unfiltered pixels disposed between the uninterrupted rows and columns. The image sensor may in CMOS with the unfiltered pixels reducing low-light noise and improving low-light sensitivity.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 5, 2007
    Inventors: John Ellis-Monaghan, Mark Jaffe, Alain Loiseau, Richard Rassel
  • Publication number: 20070145438
    Abstract: A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
    Type: Application
    Filed: March 2, 2007
    Publication date: June 28, 2007
    Inventors: James Adkisson, Andres Bryant, John Ellis-Monaghan, Jeffrey Gambino, Mark Jaffe, Jerome Lasky, Richard Phelps
  • Publication number: 20070132067
    Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10?18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.
    Type: Application
    Filed: November 8, 2006
    Publication date: June 14, 2007
    Inventors: Timothy Dalton, Jeffrey Gambino, Mark Jaffe, Stephen Luce, Edmund Sprogis
  • Publication number: 20070114622
    Abstract: A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a inner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material.
    Type: Application
    Filed: January 17, 2007
    Publication date: May 24, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Adkisson, Jeffrey Gambino, Mark Jaffe, Robert Leidy, Anthony Stamper
  • Publication number: 20070108485
    Abstract: A structure (and method for forming the same) for an image sensor cell. The method includes providing a semiconductor substrate. Then, a charge collection well is formed in the semiconductor substrate, the charge collection well comprising dopants of a first doping polarity. Next, a surface pinning layer is formed in the charge collection well, the surface pinning layer comprising dopants of a second doping polarity opposite to the first doping polarity. Then, an electrically conductive push electrode is formed in direct physical contact with the surface pinning layer but not in direct physical contact with the charge collection well. Then, a transfer transistor is formed on the semiconductor substrate. The transfer transistor includes first and second source/drain regions and a channel region. The first and second source/drain regions comprise dopants of the first doping polarity. The first source/drain region is in direct physical contact with the charge collection well.
    Type: Application
    Filed: January 2, 2007
    Publication date: May 17, 2007
    Inventors: James Adkisson, John Ellis-Monaghan, Jeffrey Gambino, Mark Jaffe, Richard Rassel
  • Publication number: 20070102738
    Abstract: The present invention provides a light shield for shielding the floating diffusion of a complementary metal-oxide semiconductor (CMOS) imager. In accordance with an embodiment of the present invention, there is provided a pixel sensor cell including: a device region formed on a substrate; and a first layer of material forming a sidewall adjacent to a side of the device region for blocking electromagnetic radiation from the device region.
    Type: Application
    Filed: November 9, 2005
    Publication date: May 10, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Adkisson, Jeffrey Gambino, Mark Jaffe
  • Publication number: 20070087463
    Abstract: A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation structure is formed adjacent to the photosensitive device pinning layer. The trench isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffiusion process whereby dopant materials present in a doped material layer formed along selected portions in the trench are driven into the underlying substrate during an anneal.
    Type: Application
    Filed: November 27, 2006
    Publication date: April 19, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Adkisson, Mark Jaffe, Robert Leidy