Abstract: A data processing apparatus comprises at least one source processor core, at least two destination processor cores, a message handler and a bus arrangement providing a data communication path between the source core, the destination cores and the message handler. The message handler has plurality of message-handling modules. At least one of the message-handling modules has a message receipt indicator that is modifiable by each of the destination processor cores to indicate that a message has been received at its destination. This message-handling module also has a transmission completion detector operable to detect, in dependence upon a message receipt indicator value that a message has been received by all of the at least two destination processor cores and to initiate transmission of an acknowledgement signal to the source processor core.

Abstract: The present invention is a high frequency detection circuit (10) which includes a high frequency filter (12) and a frequency comparator (14) which compares the output of the high frequency filter with the incoming clock signal to determine if the high frequency filter is in operation. If operating, a status register is set which a microcontroller can poll to determine if an attack has been attempted. A microcode programmer can then control what sequence of events occur once the register has been set. Alternatively, detection of operation of the high frequency filter could automatically trigger a reset or interrupt of the microcontroller.