Abstract: An inductor structure is provided that is positioned within a via of a printed circuit board. The inductor structure includes a via extending through a printed circuit board. The inductor structure includes at least one coil of an electrically conductive material beginning at a first opening to the via continuously present on a sidewall of the via encircling a center of the via extending to a second opening of the via opposite the first opening of the via. It further includes at least electrode present in contact with an end of the coil at said first or second opening.

Abstract: An inductor structure is provided that is positioned within a via of a printed circuit board. The inductor structure includes a via extending through a printed circuit board. The inductor structure includes at least one coil of an electrically conductive material beginning at a first opening to the via continuously present on a sidewall of the via encircling a center of the via extending to a second opening of the via opposite the first opening of the via. It further includes at least electrode present in contact with an end of the coil at said first or second opening.

Abstract: A method for forming passive electrical devices that includes depositing a photo reactive layer over a sidewall of a via that extends through a printed circuit board; inserting a light pipe having a mask configured to provide a passive electronic device geometry within the via to an entire depth of the via; and exposing the photo reactive layer to radiation provided by the light pipe to provide a pattern having the passive electronic device geometry on the sidewall of the via.

Abstract: Disclosed herein are solder mask formulations that include a liquid photo imagable solution and a solution of functionalized diamondoids. Also disclosed are semiconductor fabrication methods that include applying a described solder mask formulation to a semiconductor device.

Abstract: The present invention provides a process and a structure of forming conductive vias using a light guide. In an exemplary embodiment, the process includes providing a via in a base material in a direction perpendicular to a plane of the base material, applying a photoresist layer to an interior surface of the via, inserting a light guide into the via, exposing, by the light guide, a portion of the photoresist layer to light, thereby resulting in an exposed portion of the photoresist layer and an unexposed portion of the photoresist layer, removing a portion of the photoresist layer, and plating an area of the via, where the photoresist has been removed, with a metal, thereby resulting in a portion of the via plated with metal and a portion of the via not plated with metal.

Abstract: Disclosed herein are solder mask formulations that include a liquid photo imageable solution and a solution of functionalized diamondoids. Also disclosed are semiconductor fabrication methods that include applying a described solder mask formulation to a semiconductor device.

Abstract: The present invention provides a process and a structure of forming conductive vias using a light guide. In an exemplary embodiment, the process includes providing a via in a base material in a direction perpendicular to a plane of the base material, applying a photoresist layer to an interior surface of the via, inserting a light guide into the via, exposing, by the light guide, a portion of the photoresist layer to light, thereby resulting in an exposed portion of the photoresist layer and an unexposed portion of the photoresist layer, removing a portion of the photoresist layer, and plating an area of the via, where the photoresist has been removed, with a metal, thereby resulting in a portion of the via plated with metal and a portion of the via not plated with metal.

Abstract: The present invention provides a process and a structure of forming conductive vias using a light guide. In an exemplary embodiment, the process includes providing a via in a base material in a direction perpendicular to a plane of the base material, applying a photoresist layer to an interior surface of the via, inserting a light guide into the via, exposing, by the light guide, a portion of the photoresist layer to light, thereby resulting in an exposed portion of the photoresist layer and an unexposed portion of the photoresist layer, removing a portion of the photoresist layer, and plating an area of the via, where the photoresist has been removed, with a metal, thereby resulting in a portion of the via plated with metal and a portion of the via not plated with metal.

Abstract: Disclosed herein are solder mask formulations that include a liquid photo imageable solution and a solution of functionalized diamondoids. Also disclosed are semiconductor fabrication methods that include applying a described solder mask formulation to a semiconductor device.

Abstract: A method for forming passive electrical devices that includes depositing a photo reactive layer over a sidewall of a via that extends through a printed circuit board; inserting a light pipe having a mask configured to provide a passive electronic device geometry within the via to an entire depth of the via; and exposing the photo reactive layer to radiation provided by the light pipe to provide a pattern having the passive electronic device geometry on the sidewall of the via.

Abstract: Disclosed herein are solder mask formulations that include a liquid photo imageable solution and a solution of functionalized diamondoids. Also disclosed are semiconductor fabrication methods that include applying a described solder mask formulation to a semiconductor device.

Abstract: The present invention provides a process and a structure of forming conductive vias using a light guide. In an exemplary embodiment, the process includes providing a via in a base material in a direction perpendicular to a plane of the base material, applying a photoresist layer to an interior surface of the via, inserting a light guide into the via, exposing, by the light guide, a portion of the photoresist layer to light, thereby resulting in an exposed portion of the photoresist layer and an unexposed portion of the photoresist layer, removing a portion of the photoresist layer, and plating an area of the via, where the photoresist has been removed, with a metal, thereby resulting in a portion of the via plated with metal and a portion of the via not plated with metal.

Abstract: An embossed printed circuit board (PCB) for intrusion detection including a first security trace layer comprising a first serpentine trace monitored by a security sense circuit; a second security trace layer comprising a second serpentine trace monitored by the security sense circuit; a protected circuitry layer comprising circuitry protected from intrusion by the first security trace layer and the second security trace layer; and at least one embossed edge, wherein the at least one embossed edge comprises a fixed bend in at least one PCB layer, and wherein the fixed bend displaces at least one point of the at least one PCB layer a distance at least equivalent to a thickness of the at least one PCB layer.

Abstract: A method and apparatus are provided for identifying product tampering. A mechanical fastening screw, a sleeve and a movable follower disk are arranged to show evidence of tampering. The movable follower disk is received within a cavity defined by the sleeve. The sleeve includes a channel and a final resting slot defined within a sleeve wall. The movable follower disk includes compressible spring followers slideably received within the channel when the mechanical fastening screw is inserted. If the screw is removed, the compressible spring followers engage the final resting slot to indicate tampering. Electrical detection of the compressible spring followers engaging the final resting slot is used to identify tampering.

Abstract: A method and structure are provided for creating printed circuit boards with stepped thickness. A non-laminating breakaway material layer is selectively placed between layers of the printed circuit board. A perimeter portion of the printed circuit board near the breakaway material layer is scored. Then the breakaway material layer and adjacent layers between the perimeter of the printed circuit board are removed.

Abstract: A device and method for clamping and grounding a cable, includes a conductive cable clamp. The clamp is adapted to clamp and conductively engage a periphery of a conductive shield of the cable. In one aspect of the invention, the cable clamp includes a first conductive plate and a second conductive plate. Each of the plates has at least one groove formed therein. The first plate is positionable against the second plate so that the groove in the first plate and the groove in the second plate collectively form a hole extending from one edge of the cable clamp to an opposite edge of the cable clamp, with the hole accommodating the cable therein. In another aspect of the invention, the cable clamp includes a conductive flexible fabric having at least one pattern formed therein, with the pattern accommodating the cable therein.

Abstract: A shoulder strap for carrying a notebook computer is formed as an elongated member with a locking mechanism at a first end which attaches to the lock slot of the computer and a loop at the opposite end. By passing the strap through the loop, the opposite end portion of the strap is positioned around the computer adjacent the side opposite the side which includes the lock slot. With the first end of the strap secured to the computer by securing the locking mechanism at the computer lock slot, the intermediate portion of the strap extends over the users shoulder to enable transport of the computer. By forming the strap using a plastic coated steel cable, the shoulder strap may be used for both carrying the computer and as a security cable for securing the computer when unattended. The shoulder strap surfaces that engage the user's shoulder and surround and engage the notebook computer are formed of non-adhesive, non-slip material.