Abstract: The digital CMOS/LSI synchronous serial multiplier includes a register to store an X-bit sign magnitude multiplier in parallel. The digital multiplier number can be entered into the register either serially or in parallel. A serial N-bit 2's complement multiplicand input is provided. (X - 1) adder stages are connected in series. A control arrangement coupled to the register, the multiplicand input and the adder stages are provided to couple each of the magnitude bits of the multiplier number into a different one of the adder stages with the adder stages performing successive additions of the magnitude bits of the multiplier number to provide as an output of a last of the adder stages a serial product having M bits. A serial Y-bit 2's complement addend can be coupled to the first of the adder stages to add the addend to the product.