Abstract: A lossless data compressor (10) has a content addressable memory dictionary (30) and a coder (38) having between them a critical path including a feedback loop forming a dictionary on path; circuit means (42) is connected in the feedback loop so that the dictionary can be updated from a previous comparison cycle at the same time as the coder codes a current comparison cycle; and run length encoding means (46) is connected to receive the output of the coder (38). The encoding means (46) is arranged to count the number of times a match consecutively occurs at a predetermined location in the dictionary (30), that is, the number of times the same search tuple is loaded into the same address of the dictionary. Two or more lossless data compressors may be arranged in parallel in accordance with an aspect of the invention.