Patents by Inventor Mark Joseph DANCHO

Mark Joseph DANCHO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11531587
    Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: December 20, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Jun Tao, Niang-Chu Chen, Mark Joseph Dancho, Xiaoheng Chen
  • Publication number: 20210318930
    Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.
    Type: Application
    Filed: June 24, 2021
    Publication date: October 14, 2021
    Inventors: Jun TAO, Niang-Chu CHEN, Mark Joseph DANCHO, Xiaoheng CHEN
  • Patent number: 11093326
    Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: August 17, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jun Tao, Niang-Chu Chen, Mark Joseph Dancho, Xiaoheng Chen
  • Patent number: 10990304
    Abstract: The present disclosure, in various aspects, describes technologies and techniques for use by a data storage device that includes a controller of a non-volatile memory (NVM). In one example, the controller applies a default storage format to a storage region of the NVM, the default storage format configuring the storage region as a number of distinct storage regions logically arranged along a horizontal dimension and a vertical dimension. The controller modifies the default storage format using a combination of horizontal dimension scaling and vertical dimension scaling based on a performance capability of the storage region to obtain a modified storage format. The controller applies the modified storage format to the storage region.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 27, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Rodney Brittner, Xiaoheng Chen, Mark Joseph Dancho
  • Publication number: 20200409578
    Abstract: The present disclosure, in various aspects, describes technologies and techniques for use by a data storage device that includes a controller of a non-volatile memory (NVM). In one example, the controller applies a default storage format to a storage region of the NVM, the default storage format configuring the storage region as a number of distinct storage regions logically arranged along a horizontal dimension and a vertical dimension. The controller modifies the default storage format using a combination of horizontal dimension scaling and vertical dimension scaling based on a performance capability of the storage region to obtain a modified storage format. The controller applies the modified storage format to the storage region.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Rodney Brittner, Xiaoheng Chen, Mark Joseph Dancho
  • Publication number: 20200159620
    Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Jun TAO, Niang-Chu CHEN, Mark Joseph DANCHO, Xiaoheng CHEN
  • Patent number: 10558522
    Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: February 11, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jun Tao, Niang-Chu Chen, Mark Joseph Dancho, Xiaoheng Chen
  • Publication number: 20190121691
    Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.
    Type: Application
    Filed: October 20, 2017
    Publication date: April 25, 2019
    Inventors: Jun TAO, Niang-Chu CHEN, Mark Joseph DANCHO, Xiaoheng CHEN