Abstract: A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.

Abstract: An integrated circuit package includes a substrate, a flip chip die, and a capacitor. The flip chip die is attached to the substrate via die-to-substrate interconnects. The capacitor is attached to the flip chip die via capacitor-to-die interconnects so that the capacitor occupies a region between the flip chip die and the substrate. Such placement of the capacitor on a flip chip die has the advantage of reducing the distance between the capacitor and its core, thereby reducing unwanted line inductance and series resistance effects. Integrated circuit performance is thereby enhanced.

Abstract: A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.

Abstract: A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.

Abstract: An integrated circuit package includes a substrate, a flip chip die, and a capacitor. The flip chip die is attached to the substrate via die-to-substrate interconnects. The capacitor is attached to the flip chip die via capacitor-to-die interconnects so that the capacitor occupies a region between the flip chip die and the substrate. Such placement of the capacitor on a flip chip die has the advantage of reducing the distance between the capacitor and its core, thereby reducing unwanted line inductance and series resistance effects. Integrated circuit performance is thereby enhanced.

Abstract: A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.

Abstract: A frontside of a chip is bonded to a top surface of a chip carrier. Seal material is dispensed at a periphery of the top surface of the chip carrier. A solder TIM having a first side and a second side is provided. The first side of the TIM contacts a backside of the chip. A reflow is performed to melt the TIM. The second side of the TIM is bonded to a lid. The seal material is cured. The lid is attached to the top surface of the chip carrier. Backfill material is injected into a space between the top surface of the chip carrier and the lid. The backfill material abuts sides of the TIM. The backfill material is cured. TIM solder cracking and associated thermal degradation are mitigated.

Abstract: A frontside of a chip is bonded to a top surface of a chip carrier. Seal material is dispensed at a periphery of the top surface of the chip carrier. A solder TIM having a first side and a second side is provided. The first side of the TIM contacts a backside of the chip. A reflow is performed to melt the TIM. The second side of the TIM is bonded to a lid. The seal material is cured. The lid is attached to the top surface of the chip carrier. Backfill material is injected into a space between the top surface of the chip carrier and the lid. The backfill material abuts sides of the TIM. The backfill material is cured. TIM solder cracking and associated thermal degradation are mitigated.

Abstract: A method and structure is disclosed for detaching a chip from a substrate that delays the delivery of shear force to the chip until the connectors attaching the chip to the substrate are soft enough that the delivery of shear force will not damage the chip's connectors. More particularly, the shear force is created by a bimetallic disk that, when heat is applied, is transformed into shearing force. The shearing force is delayed by a delaying device until the connectors connecting the chip to the substrate are soft enough that the application of shear force will separate the chip from the substrate without damaging the chip's connectors. The delaying device includes a physical gap that may be adjusted to control when the shear force is applied to the chip.

Abstract: A method of making and the resultant micro well plate that includes a plurality of greensheets, either laminated or sintered together, whereby these greensheets have a plurality of vertical micro well reaction chamber openings therein, and optionally a plurality horizontal channels connecting selected well reaction chamber openings. The vertical micro well reaction chambers have at, at least one end thereof a plurality of optical micro plugs which are aligned to the vertical micro well reaction chamber openings. The plurality of optical micro plugs allow for the micro well plate to be integrated with macro analytical instrumentation for the analysis, examination, and/or testing of chemicals, reagents or samples provided within the vertical micro well reaction chamber openings.