Patents by Inventor Mark Kleshock

Mark Kleshock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230193502
    Abstract: A wafer plating fixture for use in simultaneously electroplating a two substrates. The wafer plating fixture including: an electrically conductive carrier bus; a plurality of contact clips electrically coupled to the carrier bus and configured to hold the two substrates in place and electrically couple the two substrates to the carrier bus; and a non-conductive substrate backer to separate the two substrates coupled to the carrier bus. A method of electroplating a plurality of substrates. The method including: mounting two substrates to be plated onto a wafer plating fixture; mounting the wafer plating fixture on a continuous belt of plating system; dipping the wafer plating fixture with the two substrates held thereon into an electroplating bath; and applying a voltage to the two substrates via the wafer plating fixture.
    Type: Application
    Filed: February 8, 2023
    Publication date: June 22, 2023
    Inventors: Hung-Ming Wang, Paul W. Loscutoff, Raphael M. Manalo, Arnold V. Castillo, Mohamad Ridzwan Mustafa, Mark A. Kleshock, Neil G. Bergstrom
  • Patent number: 11598018
    Abstract: A wafer plating fixture for use in simultaneously electroplating a two substrates. The wafer plating fixture including: an electrically conductive carrier bus; a plurality of contact clips electrically coupled to the carrier bus and configured to hold the two substrates in place and electrically couple the two substrates to the carrier bus; and a non-conductive substrate backer to separate the two substrates coupled to the carrier bus. A method of electroplating a plurality of substrates. The method including: mounting two substrates to be plated onto a wafer plating fixture; mounting the wafer plating fixture on a continuous belt of plating system; dipping the wafer plating fixture with the two substrates held thereon into an electroplating bath; and applying a voltage to the two substrates via the wafer plating fixture.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: March 7, 2023
    Assignee: SunPower Corporation
    Inventors: Hung-Ming Wang, Paul W. Loscutoff, Raphael M. Manalo, Arnold V. Castillo, Mohamad Ridzwan Mustafa, Mark A. Kleshock, Neil G. Bergstrom
  • Patent number: 11127871
    Abstract: Solar cells are attached together to form a plating assembly. The plating assembly is attached to a belt, which transports the plating assembly through a plating chamber where metal is electroplated on the solar cells. The electroplated metal is patterned to form metal contact fingers. After the metal is electroplated, the plating assembly is singulated to separate the two solar cells.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: September 21, 2021
    Assignee: SunPower Corporation
    Inventors: Paul W. Loscutoff, Hung-Ming Wang, Matthew J. Dawson, Mark A. Kleshock
  • Patent number: 10971638
    Abstract: Methods of fabricating a solar cell including metallization techniques and resulting solar cells, are described. In an example, a semiconductor region can be formed in or above a substrate. A first metal layer can be formed over the semiconductor region. A laser can be applied over a first region of the metal layer to form a first metal weld between the metal layer and the semiconductor region, where applying a laser over the first region comprises applying the laser at a first scanning speed. Subsequent to applying the laser over the first region, the laser can be applied over a second region of the metal layer where applying the laser over the second region includes applying a laser at a second scanning speed. Subsequent to applying the laser over the second region, the laser can be applied over a third region of the metal layer to form a second metal weld, where applying the laser over the third region comprises applying the laser at a third scanning speed.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: April 6, 2021
    Assignees: SunPower Corporation, Total Marketing Sendees
    Inventors: Matthieu Moors, Markus Nicht, Daniel Maria Weber, Rico Bohme, Mario Gjukic, Gabriel Harley, Mark Kleshock, Mohamed A. Elbandrawy, Taeseok Kim
  • Publication number: 20200127150
    Abstract: Solar cells are attached together to form a plating assembly. The plating assembly is attached to a belt, which transports the plating assembly through a plating chamber where metal is electroplated on the solar cells. The electroplated metal is patterned to form metal contact fingers. After the metal is electroplated, the plating assembly is singulated to separate the two solar cells.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 23, 2020
    Applicant: SunPower Corporation
    Inventors: Paul W. LOSCUTOFF, Hung-Ming WANG, Matthew J. DAWSON, Mark A. KLESHOCK
  • Publication number: 20190301047
    Abstract: A wafer plating fixture for use in simultaneously electroplating a two substrates. The wafer plating fixture including: an electrically conductive carrier bus; a plurality of contact clips electrically coupled to the carrier bus and configured to hold the two substrates in place and electrically couple the two substrates to the carrier bus; and a non-conductive substrate backer to separate the two substrates coupled to the carrier bus. A method of electroplating a plurality of substrates. The method including: mounting two substrates to be plated onto a wafer plating fixture; mounting the wafer plating fixture on a continuous belt of plating system; dipping the wafer plating fixture with the two substrates held thereon into an electroplating bath; and applying a voltage to the two substrates via the wafer plating fixture.
    Type: Application
    Filed: March 7, 2019
    Publication date: October 3, 2019
    Inventors: Hung-Ming Wang, Paul W. Loscutoff, Raphael M. Manalo, Amold V. Castillo, Mohamad Ridzwan Mustafa, Mark A. Kleshock, Neil G. Bergstrom
  • Publication number: 20180145194
    Abstract: Methods of fabricating a solar cell including metallization techniques and resulting solar cells, are described. In an example, a semiconductor region can be formed in or above a substrate. A first metal layer can be formed over the semiconductor region. A laser can be applied over a first region of the metal layer to form a first metal weld between the metal layer and the semiconductor region, where applying a laser over the first region comprises applying the laser at a first scanning speed. Subsequent to applying the laser over the first region, the laser can be applied over a second region of the metal layer where applying the laser over the second region includes applying a laser at a second scanning speed. Subsequent to applying the laser over the second region, the laser can be applied over a third region of the metal layer to form a second metal weld, where applying the laser over the third region comprises applying the laser at a third scanning speed.
    Type: Application
    Filed: January 22, 2018
    Publication date: May 24, 2018
    Inventors: Matthieu Moors, Markus Nicht, Daniel Maria Weber, Rico Bohme, Mario Gjukic, Gabriel Harley, Mark Kleshock, Mohamed A. Elbandrawy, Taeseok Kim
  • Patent number: 9882071
    Abstract: Methods of fabricating a solar cell including metallization techniques and resulting solar cells, are described. In an example, a semiconductor region can be formed in or above a substrate. A first metal layer can be formed over the semiconductor region. A laser can be applied over a first region of the metal layer to form a first metal weld between the metal layer and the semiconductor region, where applying a laser over the first region comprises applying the laser at a first scanning speed. Subsequent to applying the laser over the first region, the laser can be applied over a second region of the metal layer where applying the laser over the second region includes applying a laser at a second scanning speed. Subsequent to applying the laser over the second region, the laser can be applied over a third region of the metal layer to form a second metal weld, where applying the laser over the third region comprises applying the laser at a third scanning speed.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 30, 2018
    Assignees: SunPower Corporation, Total Marketing Services
    Inventors: Matthieu Moors, Markus Nicht, Daniel Maria Weber, Rico Bohme, Mario Gjukic, Gabriel Harley, Mark Kleshock, Mohamed A. Elbandrawy, Taeseok Kim
  • Publication number: 20180006171
    Abstract: Methods of fabricating a solar cell including metallization techniques and resulting solar cells, are described. In an example, a semiconductor region can be formed in or above a substrate. A first metal layer can be formed over the semiconductor region. A laser can be applied over a first region of the metal layer to form a first metal weld between the metal layer and the semiconductor region, where applying a laser over the first region comprises applying the laser at a first scanning speed. Subsequent to applying the laser over the first region, the laser can be applied over a second region of the metal layer where applying the laser over the second region includes applying a laser at a second scanning speed. Subsequent to applying the laser over the second region, the laser can be applied over a third region of the metal layer to form a second metal weld, where applying the laser over the third region comprises applying the laser at a third scanning speed.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Inventors: Matthieu Moors, Markus Nicht, Daniel Maria Weber, Rico Bohme, Mario Gjukic, Gabriel Harley, Mark Kleshock, Mohamed A. Elbandrawy, Taeseok Kim
  • Patent number: 7993057
    Abstract: Systems are provided for measuring temperature in a semiconductor processing chamber. Embodiments provide a multi-junction thermocouple comprising a first junction and a second junction positioned to measure temperature at substantially the same portion of a substrate. A controller may detect failures in the first junction, the second junction, a first wire pair extending from the first junction, or a second wire pair extending from the second junction. The controller desirably responds to a detected failure of the first junction or first wire pair by selecting the second junction and second wire pair. Conversely, the controller desirably responds to a detected failure of the second junction or second wire pair by selecting the first junction and first wire pair. Systems taught herein may permit accurate and substantially uninterrupted temperature measurement despite failure of a junction or wire pair in a thermocouple.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: August 9, 2011
    Assignee: ASM America, Inc.
    Inventors: Ravinder Aggarwal, Mark Kleshock, Loren Jacobs
  • Publication number: 20090159000
    Abstract: Systems are provided for measuring temperature in a semiconductor processing chamber. Embodiments provide a multi-junction thermocouple comprising a first junction and a second junction positioned to measure temperature at substantially the same portion of a substrate. A controller may detect failures in the first junction, the second junction, a first wire pair extending from the first junction, or a second wire pair extending from the second junction. The controller desirably responds to a detected failure of the first junction or first wire pair by selecting the second junction and second wire pair. Conversely, the controller desirably responds to a detected failure of the second junction or second wire pair by selecting the first junction and first wire pair. Systems taught herein may permit accurate and substantially uninterrupted temperature measurement despite failure of a junction or wire pair in a thermocouple.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Applicant: ASM AMERICA, INC.
    Inventors: Ravinder Aggarwal, Mark Kleshock, Loren Jacobs
  • Patent number: 7182816
    Abstract: Particle flaking is reduced in a semiconductor wafer processing apparatus by installing a chamber shield assembly in the chamber of the apparatus. The shield assembly includes a plurality of nested shields that are supported out of contact with each other and suspended such that, during thermal expansion and contraction, gaps are maintained that are sufficient to avoid arcing. Alignment structure on the shields and on the chamber walls force the shields to align concentrically and maintain the gaps. The shields are made of aluminum or another thermally conductive material and have cross-sectional areas large enough to provide high thermal conductivity throughout the shields. Mounting flanges and other mounting surfaces are provided on the shields that form intimate thermal contact with sufficient contacting area to insure high thermal conductivity from the shields to the temperature controlled walls of the chamber.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: February 27, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Mark Kleshock, Jacques Faguet, Tim Provencher
  • Publication number: 20050147742
    Abstract: A processing chamber component, for example, a removable chamber shield, that has a tendency to expand when exposed to a heat flux, is temperature controlled. The temperature controlled component is particularly useful where exposed to material deposits during processing by PVD, CVD and etching, for example. The component is provided with temperature control properties that avoid high temperatures and temperature gradients as well as large temperature fluctuations. In the case of a chamber shield, the shield may be formed of a base layer typically of a refractory metal such as stainless steel, which has a relatively low thermal conductivity but is mounted in contact with a heat sink, usually at one end thereof such that its other end, which is free, has a tendency to heat and partially cool from processing cycle to processing cycle. The chamber part is provided with a cladding on the base layer of a material of higher thermal conductivity than that of the base layer.
    Type: Application
    Filed: January 7, 2004
    Publication date: July 7, 2005
    Inventors: Mark Kleshock, Bruce Gittleman
  • Publication number: 20050039679
    Abstract: Particle flaking is reduced in a semiconductor wafer processing apparatus by installing a chamber shield assembly in the chamber of the apparatus. The shield assembly includes a plurality of nested shields that are supported out of contact with each other and suspended such that, during thermal expansion and contraction, gaps are maintained that are sufficient to avoid arcing. Alignment structure on the shields and on the chamber walls force the shields to align concentrically and maintain the gaps. The shields are made of aluminum or another thermally conductive material and have cross-sectional areas large enough to provide high thermal conductivity throughout the shields. Mounting flanges and other mounting surfaces are provided on the shields that form intimate thermal contact with sufficient contacting area to insure high thermal conductivity from the shields to the temperature controlled walls of the chamber.
    Type: Application
    Filed: August 18, 2003
    Publication date: February 24, 2005
    Inventors: Mark Kleshock, Jacques Faguet, Tim Provencher
  • Publication number: 20040129221
    Abstract: An improved deposition baffle, that is provided to protect a dielectric window from conductive deposits, is provided in high-density-plasma apparatus. The baffle has a central circular part having slots cut therein that are interrupted by electrically conductive bridges. Ribs in the body between the slots have cooling fluid channel sections bored therein, which are joined in series by interconnecting channel portions in a peripheral annular part of the baffle to form a continuous serpentine cooling fluid flow path from an inlet to an outlet in the annular peripheral part of the baffle.
    Type: Application
    Filed: January 8, 2003
    Publication date: July 8, 2004
    Inventors: Jozef Brcka, Mark Kleshock, Tim Provencher