Abstract: Test devices and methods for performing voltage contrast inspections on semiconductor device backside metallization regions are provided. Test devices can include a semiconductor device layer and a virtual ground layer.

Abstract: Techniques are provided herein to form an integrated circuit having backside conductive contacts beneath source or drain regions. Backside cavities beneath the source or drain regions are formed using backside lithography and anisotropic etching. The backside cavities are subsequently filled with a conductive material to form the backside contacts. A semiconductor device includes a gate structure around or otherwise on a semiconductor region that extends from a first source or drain region to a second source or drain region. The substrate beneath the semiconductor device is removed from the backside to expose a subfin region that is also removed using a backside etch and replaced with a dielectric material. Suitable lithographic operations may be performed on the backside dielectric material along with an anisotropic etch to form any number of cavities through the dielectric material. The backside conductive contacts are then formed within the backside cavities.

Abstract: Techniques are provided to form an integrated circuit having self-aligned backside contacts. The process includes frontside operations to provide dielectric plugs beneath source or drain regions that can be selectively removed from the backside of the structure. A FET (field effect transistor) includes semiconductor material extending in a first direction between source and drain regions, and a gate structure extending in a second direction around the semiconductor material. During the formation of inner dielectric spacers between the semiconductor material, some of the dielectric material remains at the bottom of source/drain trenches to form dielectric plugs that are self-aligned beneath the source or drain regions. These self-aligned dielectric plugs can be exposed from the backside following the removal of the substrate and replaced with backside conductive contacts that are self-aligned beneath the source or drain regions. A dielectric liner may also be provided over the dielectric plugs.

Abstract: Integrated circuit structures having contact to links for uniform grid metal gate and trench contact cut are described. A structure includes a dielectric sidewall spacer between a gate electrode and a conductive trench contact. First and second parallel dielectric cut plug structures extend through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The second dielectric cut plug has a recess laterally adjacent to first and second portions of the conductive trench contact. A conductive link is in the recess of the second dielectric cut plug structure, the conductive link connecting the first and second portions of the conductive trench contact. A conductive via is on the conductive link and overlaps the first and second portions of the conductive trench contact.

Abstract: Integrated circuit structures having contacts for uniform grid metal gate and trench contact cut are described. A structure includes a dielectric sidewall spacer between a gate electrode and a conductive trench contact. A dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A dielectric cap layer covers the dielectric sidewall spacer and the dielectric cut plug structure, and exposes a portion of the gate electrode and a portion of the conductive trench contact. A conductive via is in contact with the portion of the gate electrode or the portion of the conductive trench contact. The conductive via overlaps a top surface of the dielectric cap layer.

Abstract: Techniques are provided herein for forming a via with an asymmetrically flared profile within the interconnect region over semiconductor devices. In some examples, a via within the interconnect layer has a greater critical dimension (CD), or top surface width, along a first direction (e.g., along an X-axis) than it has along a second direction orthogonal to the first direction (e.g., along a Y-axis). The bottom surface of the via may have substantially the same width along both the first and second directions, such that the width of the via tapers or steps inward between the top surface width along the first direction and the bottom surface width along the first direction. There is little to no tapering or step of the via between the top surface width along the second direction and the bottom surface width along the second direction.

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a first conductive interconnect line in a first inter-layer dielectric (ILD) layer above a substrate, the first conductive interconnect line along a first direction. A second conductive interconnect line is in a second ILD layer above the first ILD layer, the second conductive interconnect line along a second direction orthogonal to the first direction. A conductive via is coupling the first conductive interconnect line and the second conductive interconnect line, the conductive via inwardly tapered from a top to a bottom of the conductive via along curved sidewalls along the second direction but not along the first direction, and the conductive via contiguous with but not continuous with the second conductive interconnect line.

Abstract: Selective dielectric growth directing contact to gate or contact to trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures and have an uppermost surface above an uppermost surface of gate electrodes of the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures. A dielectric-on-metal (DOM) layer is on and is confined to the uppermost surface of the conductive trench contact structures. A gate contact via is on a gate electrode of one of the plurality of gate structures.

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a first conductive interconnect line in a first inter-layer dielectric (ILD) layer above a substrate, a second conductive interconnect line in a second ILD layer above the first ILD layer, and a conductive via coupling the first conductive interconnect line and the second conductive interconnect line, the conductive via having a single, nitrogen-free tantalum (Ta) barrier layer. In another example, a method of fabricating an integrated circuit structure includes forming a partial trench in an inter-layer dielectric (ILD layer, the ILD layer on an etch stop layer, etching a hanging via that lands on the etch stop layer, and performing a breakthrough etch through the etch stop layer to form a trench and via opening in the ILD layer and the etch stop layer.