Abstract: A method including accessing a first virtual prototype configured to perform a first simulation of a hardware design, identifying checkpoints within the first virtual prototype, each checkpoint including a storage state and/or behavioral state, and determining breakpoints for dividing execution of a second virtual prototype into a series of execution segments, where the second virtual prototype is configured to perform a second simulation of the hardware design, the second virtual prototype includes virtual models representing a separate portion of the hardware design, each virtual model representing a same portion of the hardware design as a corresponding virtual model of the first virtual prototype.

Abstract: A method including accessing a first virtual prototype configured to perform a first simulation of a hardware design, identifying checkpoints within the first virtual prototype, each checkpoint including a storage state and/or behavioral state, and determining breakpoints for dividing execution of a second virtual prototype into a series of execution segments, where the second virtual prototype is configured to perform a second simulation of the hardware design, the second virtual prototype includes virtual models representing a separate portion of the hardware design, each virtual model representing a same portion of the hardware design as a corresponding virtual model of the first virtual prototype.

Abstract: System and methods for monitoring software simulations of hardware devices optimize the monitoring of a hardware system by comparing a current software state to previously stored patterns of software states in order to disable portions of the simulation.

Abstract: A system-level description that specifies functions performed by the components and interactions thereamong is divided into a plurality of functional blocks, each corresponding to a component. At least one of the functional blocks is selectively replaced with an optimized equivalent functional block, and the functional blocks and the at least one optimized equivalent functional block are interconnected in a manner consistent with the system-level description.

Abstract: A system-level simulation of hardware devices, each of which may have different timing requirements, utilizes one or more master objects and update objects (e.g., a clock object) in order to coordinate the device simulations. The master object may, for example, advance the update objects according to one or more criteria and then instruct an object representing a hardware device to execute.

Abstract: Integration of a system-level simulation with one or more hardware device simulations is accomplished using a mapping layer, which allows the system-level simulation to interact with the hardware device simulation at a pin level, an object level, and an abstract level. The overall simulation may operate with respect to a clock or timing device or it may operate with respect to transactions.

Abstract: A system-level simulation of hardware devices utilizes interconnection objects to facilitate communication between a simulated device and the system, or between different simulated devices. A device may send output data to the interconnection object and/or receive input from the interconnection object. Additionally, the interconnection object may have some data-validation capability for incoming and outgoing data.