Patents by Inventor Mark KRAMAN

Mark KRAMAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-volatile memory array with integrated memory and access transistors and method of making the same
    Patent number: 12725639
    Abstract: A device structure includes base semiconductor rail structures overlying a semiconductor substrate, bottom bit lines contacting a sidewall of a respective one of the base semiconductor rail structures, a two-dimensional array of lower semiconductor pillars, lower gate electrode lines overlying the bottom bit lines and laterally spaced from sidewall segments of a respective column of the lower semiconductor pillars by a lower gate dielectric layer, a two-dimensional array of upper semiconductor pillars, upper gate electrode lines overlying the lower gate electrode lines and laterally spaced from sidewall segments of a respective column of the upper semiconductor pillars by an upper gate dielectric layer, and at least one top bit line contacting top surfaces of a respective row of upper semiconductor pillars.
    Type: Grant
    Filed: September 6, 2024
    Date of Patent: September 1, 2026
    Assignee: Sandisk Technologies, Inc.
    Inventors: Mark Kraman, Kartik Sondhi, Peng Zhang, Johann Alsmeier, Senaka Kanakamedala, Yan Li
  • HIGH BANDWIDTH BONDED ASSEMBLY WITH THROUGH-SUBSTRATE VIA STRUCTURES SHIELDED BY GUARD RINGS AND METHODS FOR FORMING THE SAME
    Publication number: 20260130282
    Abstract: A semiconductor structure includes a first unit bonded assembly including a first memory die bonded to a first logic die by direct copper to copper bonding, where that the first logic die includes first through-substrate via structures laterally surrounded by first doped semiconductor well guard rings, and a second unit bonded assembly including a second memory die bonded to a second logic die by direct copper to copper bonding. The first unit bonded assembly is bonded to a second unit bonded assembly by solder balls.
    Type: Application
    Filed: November 7, 2024
    Publication date: May 7, 2026
    Inventors: Guangyuan LI, Mark KRAMAN, Fumiaki TOYAMA
  • NON-VOLATILE MEMORY ARRAY WITH INTEGRATED MEMORY AND ACCESS TRANSISTORS AND METHOD OF MAKING THE SAME
    Publication number: 20260073951
    Abstract: A device structure includes base semiconductor rail structures overlying a semiconductor substrate, bottom bit lines contacting a sidewall of a respective one of the base semiconductor rail structures, a two-dimensional array of lower semiconductor pillars, lower gate electrode lines overlying the bottom bit lines and laterally spaced from sidewall segments of a respective column of the lower semiconductor pillars by a lower gate dielectric layer, a two-dimensional array of upper semiconductor pillars, upper gate electrode lines overlying the lower gate electrode lines and laterally spaced from sidewall segments of a respective column of the upper semiconductor pillars by an upper gate dielectric layer, and at least one top bit line contacting top surfaces of a respective row of upper semiconductor pillars.
    Type: Application
    Filed: September 6, 2024
    Publication date: March 12, 2026
    Inventors: Mark KRAMAN, Kartik SONDHI, Peng ZHANG, Johann ALSMEIER, Senaka KANAKAMEDALA, Yan LI