Abstract: The present invention provides methods for executing instructions in a processor to facilitate the debugging of digital systems. In these methods, a halt identifier field is associated with every instruction that holds an encoding specifying an action to be performed by a processor. As instructions are executed on a processor, actions are performed by the processor based on the value of the halt identifier field of the executed instructions. In an embodiment, when each instruction is executed, the contents of the halt identifier field are compared to a pre-selected identifier value and the processor is halted if the values are the same. In a multiprocessor system, the pre-selected identifier may be a unique value that identifies the processor such that when the halt identifier field is equal to that value, the processor will halt.

Abstract: Systems and methods of adjusting synchronization of audio media streams and video media streams in 3G mobile communications systems that can mitigate the effects of temporal skew due to intervening processing elements associated with media channels carrying the respective media streams. The systems and methods are operative to adjust the synchronization of audio media streams and video media streams by receiving control messages that report delays due to such intervening processing elements, calculating a relative amount of delay using the reported delays for each media channel, and applying a delay factor based on the relative amount of delay to the faster media channel to place the audio media streams and the video media streams in proper temporal alignment. The delay factor is applied to the faster media channel at those locations within the mobile communications systems where the audio and video media streams are combined and/or separated for subsequent transmission.

Abstract: Systems and methods of adjusting synchronization of audio media streams and video media streams in 3G mobile communications systems that can mitigate the effects of temporal skew due to intervening processing elements associated with media channels carrying the respective media streams. The systems and methods are operative to adjust the synchronization of audio media streams and video media streams by receiving control messages that report delays due to such intervening processing elements, calculating a relative amount of delay using the reported delays for each media channel, and applying a delay factor based on the relative amount of delay to the faster media channel to place the audio media streams and the video media streams in proper temporal alignment. The delay factor is applied to the faster media channel at those locations within the mobile communications systems where the audio and video media streams are combined and/or separated for subsequent transmission.

Abstract: The invention relates to a method for transparently maintaining cache coherency when debugging a multiple processor system with common shared memory. A software memory map representing the memory usage of the processors in the system to be debugged is created and in the software memory map is an indication of whether or not each processor has a cache. At least two debug sessions associated with two processors are activated. If an active debug session requests a write to a shared memory location, the request is executed and the software memory map is searched to located all processors having read access to that shared memory location. The write request is broadcast to each of the located processors so that each processor can perform any required cache updates.

Abstract: The invention relates to a method for transparently writing to shared memory when debugging a multiple processor system. In this method, a software memory map reflecting the memory usage of the processors in the system to be debugged is created. Two or more debug sessions associated with processors in the system are activated. When a debug session makes a write request to a shared memory location, a check is made to see if the processor associated with that debug session has write access to the shared memory location. If it does, that processor is used to execute the write. If it does not, the software memory map is searched to find a processor that does have write access to the shared memory location and that processor is used to execute the write.

Abstract: The invention relates to a method for maintaining coherency of software breakpoints in shared memory when debugging a multiple processor system. Using this method, at least two debug sessions associated with processors in the multiple processor system are activated. When a debug sessions sets a software breakpoint in a shared memory location, all active debug sessions are notified that the software breakpoint has been set. And, when a software breakpoint in shared memory is cleared by a debug session, all active debug sessions are notified that the software breakpoint has been removed.

Abstract: The invention relates to a method for transparently maintaining cache coherency when debugging a multiple processor system with common shared memory. A software memory map representing the memory usage of the processors in the system to be debugged is created and in the software memory map is an indication of whether or not each processor has a cache. At least two debug sessions associated with two processors are activated. If an active debug session requests a write to a shared memory location, the request is executed and the software memory map is searched to located all processors having read access to that shared memory location. The write request is broadcast to each of the located processors so that each processor can perform any required cache updates.

Abstract: The present invention provides methods for executing instructions in a processor to facilitate the debugging of digital systems. In these methods, a halt identifier field is associated with every instruction that holds an encoding specifying an action to be performed by a processor. As instructions are executed on a processor, actions are performed by the processor based on the value of the halt identifier field of the executed instructions. In an embodiment, when each instruction is executed, the contents of the halt identifier field are compared to a pre-selected identifier value and the processor is halted if the values are the same. In a multiprocessor system, the pre-selected identifier may be a unique value that identifies the processor such that when the halt identifier field is equal to that value, the processor will halt.

Abstract: The invention relates to a method for transparently maintaining cache coherency when debugging a multiple processor system with common shared memory. A software memory map representing the memory usage of the processors in the system to be debugged is created and in the software memory map is an indication of whether or not each processor has a cache. At least two debug sessions associated with two processors are activated. If an active debug session requests a write to a shared memory location, the request is executed and the software memory map is searched to located all processors having read access to that shared memory location. The write request is broadcast to each of the located processors so that each processor can perform any required cache updates.

Abstract: The invention relates to a method for transparently maintaining cache coherency when debugging a multiple processor system with common shared memory. A software memory map representing the memory usage of the processors in the system to be debugged is created and in the software memory map is an indication of whether or not each processor has a cache. At least two debug sessions associated with two processors are activated. If an active debug session requests a write to a shared memory location, the request is executed and the software memory map is searched to located all processors having read access to that shared memory location. The write request is broadcast to each of the located processors so that each processor can perform any required cache updates.

Abstract: The invention relates to a method for maintaining coherency of software breakpoints in shared memory when debugging a multiple processor system. Using this method, at least two debug sessions associated with processors in the multiple processor system are activated. When a debug sessions sets a software breakpoint in a shared memory location, all active debug sessions are notified that the software breakpoint has been set. And, when a software breakpoint in shared memory is cleared by a debug session, all active debug sessions are notified that the software breakpoint has been removed.

Abstract: The invention relates to a method for transparently writing to shared memory when debugging a multiple processor system. In this method, a software memory map reflecting the memory usage of the processors in the system to be debugged is created. Two or more debug sessions associated with processors in the system are activated. When a debug session makes a write request to a shared memory location, a check is made to see if the processor associated with that debug session has write access to the shared memory location. If it does, that processor is used to execute the write. If it does not, the software memory map is searched to find a processor that does have write access to the shared memory location and that processor is used to execute the write.