Abstract: A high speed interconnect network for a relatively large number of processors from as few as five to a hundred or more where the information transfers are serial-by-byte in a time multiplexed manner so that when one or more processors is ready to transmit, there will be an information byte being transmitted every clock time. A bus arbiter controls access to a local bus in a round-robin fashion when one or more than one processor is requesting access to the local bus. The bus arbiter also serves for connection to an overall global loop of bus arbiters each of which has a local bus and a plurality of individual processors.

Abstract: This disclosure relates to a line driver circuit for a station in a data transmission network, which driver circuit is adapted to drive the channel medium with a constant current so that conflicts or collisions with data transmissions from other stations will be cancelled out thereby preventing any particular station from dominating reception of a neighboring station. Each station is adapted to operate in a cyclic mode for contending for access to the network channel where a three-state cycle is employed, which states are the idle state, the packet-being-transmitted state and the acknowledgment period state. Each station will not begin transmission until it determines that the tunnel is in an idle state. Once the station has determined that the channel is idle, it will then delay for a period of time that is randomly chosen and, if the channel is still idle, will then begin transmission.

Abstract: This disclosure relates to a station for a data transmission network which is adapted to operate in a cyclic mode for contending for access to the network channel along with other stations of the network. The three states of the cycle are the idle state, the packet-being-transmitted state and the acknowlegement period state. Each station will not begin transmission until it determines that the channel is in an idle state. Once the station has determined that the channel is idle, it will then delay for a period of time that is randomly chosen and, if the channel is still idle, will then begin transmission. In this way, contention conflicts between stations is minimized without unduly restricting communication between stations. Following transmission, the channel will again be quiescent a short period of time before the acknowledgement signal is transmitted from the receiver.

Abstract: Improved means and methods are described for providing microprogramming in a microprogrammed data processor. A separate, relatively fast access Read/Write microinstruction memory is provided which operates as an index-associative cache memory with respect to the processor main memory in a manner which permits a high "hit" ratio to be obtained for requested microinstructions, while at the same time removing the burden from the programmer of having to be concerned with the loading and/or current contents of the microinstruction memory.