Abstract: A peak and valley detection system and method are shown for a selective call receiving device (10). The peak and valley detection system quickly and accurately detects and tracks to the peak and valley of a two level and/or four-level signal. A signal value representing a received signal is compared by a CPU (28) to the sum of a peak variable and attack constant. The peak variable is updated to a first value if the received signal value is less than the sum and is updated to a second value if the received signal value is not less than the sum. Similarly, the received signal is compared by the CPU (28) to a difference between a valley variable and attack constant. The valley variable is updated to a third value if the received signal value is greater than the difference value and updated to a fourth value if the received signal value is not greater than the difference value. The peak and valley variables attack and decay at non-constant rates and independently of one another.

Abstract: In a device having a primary battery 10, a first voltage multiplier 20 is used to power digital electrical circuits 40 from the primary battery, and a second voltage multiplier 100-136 is used to recharge a backup battery 50 from the primary battery. The backup battery is charged to a voltage greater than the voltage generated by the first voltage multiplier. Methods of controlling the second voltage multiplier reduce its interference in measurement of device parameters, and reduce the power consumed from the primary battery.

Abstract: A data recovery device (208) for recovering data symbols having a period T from a received data stream. The data recovery device samples at least one data symbol in the received data stream at a rate determined by an integration envelope (301) having the period T. The samples are accumulated as a weighted sample count representing a recovered data symbol that is then stored as at least one recovered data bit.

Abstract: A paging receiver capable of bit synchronizing to one of two data rates. The receiver has a digital phase locked loop integrated onto a single integrated circuit clocked by a single frequency crystal. The paging receiver receives and synchronizes to a POCSAG signal which may be transmitted at either 512 bits per second or 1200 bits per second. The digital phase locked loop bit synchronizes to either data rate using a single crystal frequency of 76.8 kHz. The data rate is selected by a bit in the code paging receiver's code plug. The digital phase locked loop is constructed to have a substantially constant frequency to bandwidth ratio at both data rates.

Abstract: A battery saving apparatus for supplying power to a selective call communication receiver for enabling the detection of a synchronization codeword in data received in a predetermined signaling format comprises circuits for supplying power to the receiver, and for detecting valid data received during a first portion of the first predetermined time interval. Power is maintained to the receiver for the remainder of the first predetermined time interval when valid data is detected in the first portion. A synchronization codeword detector is included for detecting a synchronization codeword. When valid data is subsequently detected following a second portion of the first predetermined time interval and the synchronization codeword is not detected in the first predetermined time interval, power is maintained to the receiver for a second predetermined time interval to further enable detection of the synchronization codeword.