Abstract: Digital circuits increase reliability of a decoder for differential phase-shift keyed signals. A tapped delay line delays the input signal by a variable amount, substantially equal to one bit time of the modulated data, and provides the delayed signal to a multiplier for generating a product signal. In response to changes in frequency of the input signal, a control system selects different taps of the delay line to provide the delayed signal for multiplication by the modulated input signal. The control signal includes a feedback loop, wherein a phase difference between the signal at the selected tap and the input signal is used to change a count in an up/down counter. A tap selecting multiplexer provides an output from specified taps in response to particular values of the count.