Patents by Inventor Mark L. Rinehimer
Mark L. Rinehimer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9509227Abstract: In a general aspect, a bridge circuit can include a first bridge including a first plurality of MOSFETs and including a first input terminal and a second input terminal, and a second bridge including a second plurality of MOSFETs and including a third input terminal and a fourth input terminal. The first bridge and the second bridge can be coupled in parallel and being coupled to a first load terminal and a second load terminal.Type: GrantFiled: January 9, 2015Date of Patent: November 29, 2016Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Scott Pearson, Mark L. Rinehimer, Sungjin Kuen
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Publication number: 20150194906Abstract: In a general aspect, a bridge circuit can include a first bridge including a first plurality of MOSFETs and including a first input terminal and a second input terminal, and a second bridge including a second plurality of MOSFETs and including a third input terminal and a fourth input terminal. The first bridge and the second bridge can be coupled in parallel and being coupled to a first load terminal and a second load terminal.Type: ApplicationFiled: January 9, 2015Publication date: July 9, 2015Inventors: Joseph A. YEDINAK, Scott PEARSON, Mark L. RINEHIMER, Sungjin KUEN
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Publication number: 20150187873Abstract: A power device includes an active region and a termination region surrounding the active region. A plurality of pillars of first and second conductivity type are alternately arranged in each of the active and termination regions. The pillars of first conductivity type in the active and termination regions have substantially the same width, and the pillars of second conductivity type in the active region have a smaller width than the pillars of second conductivity type in the termination region so that a charge balance condition in each of the active and termination regions results in a higher breakdown voltage in the termination region than in the active region.Type: ApplicationFiled: January 5, 2015Publication date: July 2, 2015Inventors: Joseph A. Yedinak, Jaegil Lee, Hocheol Jang, Chongman Yun, Praveen Muraleedharan Shenoy, Christopher L. Rexer, Changwook Kim, Jonghun Lee, Jasong M. Higgs, Dwayne S. Reichl, Joelle Sharp, Qi Wang, Yongsub Kim, Jungkil Lee, Mark L. Rinehimer, Jinyoung Jung
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Publication number: 20150069567Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.Type: ApplicationFiled: September 19, 2014Publication date: March 12, 2015Inventors: Joseph A. Yedinak, Christopher L. Rexer, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Hamza Yilmaz, Chongman Yun, Dwayne S. Reichl, James Pan, Rodney S. Ridley, Harold Heidenreich
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Publication number: 20140264569Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.Type: ApplicationFiled: March 11, 2014Publication date: September 18, 2014Applicant: Fairchild Semiconductor CorporationInventors: Joseph A. YEDINAK, Dean E. PROBST, Richard STOKES, Suku KIM, Jason HIGGS, Fred SESSION, Hui CHEN, Steven P. SAPP, Jayson PREECE, Mark L. Rinehimer
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Patent number: 8836028Abstract: In a general aspect, a power device can include at least one N-type epitaxial layer disposed on a substrate and a plurality of N-pillars and P-pillars that define alternating P-N-pillars in the at least one N-type epitaxial layer. The power device can also include an active region and a termination region, where the termination region surrounds the active region. The alternating P-N-pillars can be disposed in both the active region and the termination region, where the termination region can include a predetermined number of floating P-pillars.Type: GrantFiled: April 27, 2011Date of Patent: September 16, 2014Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Dwayne S. Reichl, Harold Heidenreich
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Patent number: 8772868Abstract: A power device includes a semiconductor substrate having a plurality of alternately arranged pillars of first and second conductivity types. At least one of the plurality of pillars of second conductivity type includes a first trench epitaxial layer of the second conductivity type disposed on a trench sidewall of the second trench and a trench bottom surface of the second trench, a second trench epitaxial layer of the second conductivity type disposed on the first trench epitaxial layer of the second conductivity type, and an insulating material layer disposed on the second trench epitaxial layer of the second conductivity type.Type: GrantFiled: April 27, 2011Date of Patent: July 8, 2014Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Hamza Yilmaz, James Pan, Rodney S. Ridley, Sr.
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Patent number: 8673700Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.Type: GrantFiled: April 27, 2011Date of Patent: March 18, 2014Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Mark L. Rinehimer, Praveen Muraleedharan Shenoy
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Patent number: 8502313Abstract: This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.Type: GrantFiled: April 21, 2011Date of Patent: August 6, 2013Assignee: Fairchild Semiconductor CorporationInventors: Rohit Dikshit, Mark L. Rinehimer, Michael D. Gruenhagen, Joseph A. Yedinak, Tracie Petersen, Ritu Sodhi, Dan Kinzer, Christopher L. Rexer, Fred C. Session
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Patent number: 8492837Abstract: Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.Type: GrantFiled: October 27, 2011Date of Patent: July 23, 2013Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Mark L. Rinehimer, Thomas E. Grebs, John L. Benjamin
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Publication number: 20120273884Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Inventors: Joseph A. Yedinak, Christopher L. Rexer, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Hamza Yilmaz, Chongman Yun, Dwayne S. Reichl, James Pan, Rodney S. Ridley, SR., Harold Heidenreich
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Publication number: 20120273875Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Inventors: Joseph A. Yedinak, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Hamza Yilmaz, James Pan, Rodney S. Ridley
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Publication number: 20120273916Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Inventors: Joseph A. Yedinak, Christopher L. Rexer, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Hamza Yilmaz, Chongman Yun, Dwayne S. Reichl, James Pan, Rodney S. Ridley, SR., Harold Heidenreich
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Publication number: 20120276701Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Inventors: Joseph A. Yedinak, Mark L. Rinehimer, Praveen Muraleedharan Shenoy
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Publication number: 20120267714Abstract: This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.Type: ApplicationFiled: April 21, 2011Publication date: October 25, 2012Inventors: Rohit Dikshit, Mark L. Rinehimer, Michael D. Gruenhagen, Joseph A. Yedinak, Tracie Petersen, Ritu Sodhi, Dan Kinzer, Christopher L. Rexer, Fred Session
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Publication number: 20120037982Abstract: Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.Type: ApplicationFiled: October 27, 2011Publication date: February 16, 2012Inventors: Joseph A. Yedinak, Mark L. Rinehimer, Thomas E. Grebs, John L. Benjamin
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Patent number: 8049276Abstract: Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.Type: GrantFiled: June 12, 2009Date of Patent: November 1, 2011Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Mark L. Rinehimer, Thomas E. Grebs, John L. Benjamin
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Publication number: 20100314707Abstract: Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.Type: ApplicationFiled: June 12, 2009Publication date: December 16, 2010Inventors: Joseph A. Yedinak, Mark L. Rinehimer, Thomas E. Grebs, John L. Benjamin
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Patent number: 6831329Abstract: A quick punch-through integrated gate bipolar transistor (IGBT) includes a drift region and a gate. The drift region has a drift region dopant concentration and a drift region thickness. The gate has a gate capacitance. The drift region dopant concentration, drift region thickness and gate capacitance are adjusted dependent at least in part upon the PNP gain of the IGBT to maintain the potential difference between the gate and emitter at a level greater than the IGBT threshold voltage when the collector voltage reaches the bus voltage. This insures that the hole carrier concentration remains approximately equal to or greater than the drift region dopant concentration when the depletion layer punches through to the buffer region during the turn-off delay. Thus, the collector voltage overshoot and the rate of change of voltage and current are controlled, and electromagnetic interference is reduced, during turn off.Type: GrantFiled: October 22, 2002Date of Patent: December 14, 2004Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Jon Gladish, Sampat Shekhawat, Gary M. Dolny, Praveen Muraleedharan Shenoy, Douglas Joseph Lange, Mark L. Rinehimer
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Publication number: 20030080377Abstract: A quick punch-through integrated gate bipolar transistor (IGBT) includes a drift region and a gate. The drift region has a drift region dopant concentration and a drift region thickness. The gate has a gate capacitance. The drift region dopant concentration, drift region thickness and gate capacitance are adjusted dependent at least in part upon the PNP gain of the IGBT to maintain the potential difference between the gate and emitter at a level greater than the IGBT threshold voltage when the collector voltage reaches the bus voltage. This insures that the hole carrier concentration remains approximately equal to or greater than the drift region dopant concentration when the depletion layer punches through to the buffer region during the turn-off delay. Thus, the collector voltage overshoot and the rate of change of voltage and current are controlled, and electromagnetic interference is reduced, during turn off.Type: ApplicationFiled: October 22, 2002Publication date: May 1, 2003Inventors: Joseph A. Yedinak, Jon Gladish, Sampat Shekhawat, Gary M. Dolny, Praveen Muraleedharan Shenoy, Douglas Joseph Lange, Mark L. Rinehimer