Abstract: A low latency digital clock fault detector has an edge detector including a delay line generating pulses on edges o an incoming clock signal of a width determined by the length of said delay line. A watchdog timer with flip-flops in a pipeline configuration has a first input held at a static logic level, a second input receiving a reference clock, and a third reset input. The watchdog is being responsive to the pulses to maintain a stable output in the presence of said pulses and generate a fault indication in the absence of the pulses.

Abstract: A low latency digital clock fault detector has an edge detector including a delay line generating pulses on edges o an incoming clock signal of a width determined by the length of said delay line. A watchdog timer with flip-flops in a pipeline configuration has a first input held at a static logic level, a second input receiving a reference clock, and a third reset input. The watchdog is being responsive to the pulses to maintain a stable output in the presence of said pulses and generate a fault indication in the absence of the pulses.

Abstract: A secure electronic data module containing a monolithic semiconductor chip of the type having a memory that is protected by a combination of hardware and software mechanisms such that unauthorized access to the data stored in the memory is prevented. The monolithic semiconductor chip comprises a plurality of solder bumps for attaching the chip to a substrate that may be a printed circuit board or another chip; a multi-level interlaced power and ground lines using minimum geometries; and a detection circuit block for detecting an external trip signal that may be produced by a pre-specified change in an operating condition brought on by unauthorized accessing, or an internal trip signal that may be produced by shorting of power and ground lines or by a change in an oscillator's frequency, also associated with or appurtenant to unauthorized accessing of the secure memory.

Abstract: An integrated circuit terminator for a SCSI bus with resistors made of laser-blowable fuses in an array and a reference voltage source made with a bandgap generator and a two stage amplifier including a dummy isolation stage for providing symmetrical mismatch currents.

Abstract: An integrated circuit terminator for a SCSI bus with resistors made of laser-blowable fuses in an array and a reference voltage source made with a bandgap generator and a two stage amplifier including a dummy isolation stage for providing symmetrical mismatch currents.