Patents by Inventor Mark Layne Shaw

Mark Layne Shaw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7242285
    Abstract: A system (10) and method manages battery (13) power in a wheel module (11) for indicating when air pressure in a tire falls below a recommended value. Tire air pressure is sensed with a pressure sensor (16). Tire air temperature is sensed with a temperature sensor (18). A determination is made whether the air pressure is increasing or decreasing with respect to time. Based upon whether a ratio of the air pressure and the air temperature is increasing, decreasing or remaining constant with respect to time, tire motion is inferred without directly sensing acceleration or movement of the tire. Power management circuitry (14) controls battery power to enable sensing of air pressure and air temperature at measurement intervals that are longer in time when the tire is not in motion.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: July 10, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Mark Layne Shaw
  • Patent number: 4066876
    Abstract: A digital speed control system includes a first binary up-counter called an Actual Count Register. The Actual Count Register is initially reset to contain all "0"'s. During a sample time, an input is applied to the Actual Count Register so that it counts up to a first binary number during the sample time. The first binary number represents a reference speed. The system includes a Reference Count Register. In response to read and store command, the first binary number is loaded into the Reference Count Register, where it remains until the next request for a new reference speed. The system further includes a first binary presettable up-counter called the Error Register. The Error Register counts up at the same rate and in response to the same count signal as the Actual Count Register. During a Transfer signal which follows the Read signal, the complement of the first binary number is transferred from the Reference Count Register into the Error Register.
    Type: Grant
    Filed: July 8, 1976
    Date of Patent: January 3, 1978
    Assignee: Motorola, Inc.
    Inventors: Mark Layne Shaw, Howard Fredrick Weber
  • Patent number: 4066874
    Abstract: A digital speed control system includes a first binary up-counter called an Actual Count Register. The Actual Count Register is initially reset to contain all "0"'s. During a sample time, an input is applied to the Actual Count Register so that it counts up to a first binary number during the sample time. The first binary number represents a reference speed. The system includes a Reference Count Register. In response to read and store command, the first binary number is loaded into the Reference Count Register, where it remains until the next request for a new reference speed. The system further includes a first binary presettable up-counter called the Error Register. The Error Register counts up at the same rate and in response to the same count signal as the Actual Count Register. During a Transfer signal which follows the Read signal, the complement of the first binary number is transferred from the Reference Count Register into the Error Register.
    Type: Grant
    Filed: July 8, 1976
    Date of Patent: January 3, 1978
    Assignee: Motorola, Inc.
    Inventor: Mark Layne Shaw
  • Patent number: 4031477
    Abstract: A zener diode and resistor network is coupled to a single conductor by a switching device which, in combination with the network, produces a voltage on the conductor representative of one of four commands selected by the switching device. Another zener diode and resistor network is coupled to the receiving end of the transmission conductor and operates to generate two ternary signals which, in combination, are representative of the selected command. A plurality of dual-threshold CMOS logic gates generates four binary output signals responsive to the two ternary signals.
    Type: Grant
    Filed: April 26, 1976
    Date of Patent: June 21, 1977
    Assignee: Motorola, Inc.
    Inventor: Mark Layne Shaw