Abstract: Described herein are methods for accessing a block-based storage device having a memory-mapped interface and a block interface. In one embodiment, an apparatus (e.g., block-based storage device) includes a storage array to store data and a memory-mapped interface that is coupled to the storage array. The memory-mapped interface includes memory-mapped memory space. The memory-mapped interface receives direct access requests from a host to directly access memory-mapped files. The apparatus also includes a block interface that is coupled to the storage array. The block interface receives block requests from a storage driver to access the storage array.

Abstract: Described herein are methods for accessing a block-based storage device having a memory-mapped interface and a block interface. In one embodiment, an apparatus (e.g., block-based storage device) includes a storage array to store data and a memory-mapped interface that is coupled to the storage array. The memory-mapped interface includes memory-mapped memory space. The memory-mapped interface receives direct access requests from a host to directly access memory-mapped files. The apparatus also includes a block interface that is coupled to the storage array. The block interface receives block requests from a storage driver to access the storage array.

Abstract: Subject matter disclosed herein relates to a user-switchable error correction coding (ECC) engine residing on a memory die.

Abstract: Subject matter disclosed herein relates to a user-switchable error correction coding (ECC) engine residing on a memory die.

Abstract: Subject matter disclosed herein relates to a user-switchable error correction coding (ECC) engine residing on a memory die.

Abstract: Subject matter disclosed herein relates to a user-switchable error correction coding (ECC) engine residing on a memory die.

Abstract: A memory device may comprise a port to receive remap information regarding a memory device and may comprise a content-addressable memory (CAM) to store the remap information, wherein the CAM may comprise a nonvolatile, discretely-addressable memory.

Abstract: Disparate nonvolatile memory types are included in a system. Writes are performed in a first type of nonvolatile memory when the size of the write is below a threshold, and are performed in a second type of nonvolatile memory when the size of the write is above the threshold. The threshold may be a number of sectors. The disparate memory types may include FLASH memory and phase change memory (PCM).

Abstract: An autonomous memory device in a distributed memory sub-system can receive a database downloaded from a host controller. The autonomous memory device can pass configuration routing information and initiate instructions to disperse portions of the database to neighboring die using an interface that handles inter-die communication. Information is then extracted from the pool of autonomous memory and passed through a host interface to the host controller.

Abstract: An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem and re-allocates resources based on the monitored results to dynamically improve system performance.

Abstract: Subject matter disclosed herein relates to remapping memory devices.

Abstract: A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for autonomous memory subsystems in computing platforms. In some embodiments, the autonomous memory mechanism includes one or more autonomous memory logic instances (AMLs) and a transaction protocol to control the AMLs. The autonomous memory mechanism can be employed to accelerate bulk memory operations. Other embodiments are described and claimed.

Abstract: Described herein are one or more implementations that eliminate the need to switch data-resource access-modes of a flash memory system between a primary main array memory and a secondary supernumerary data resource. The one or more described implementations provide access to the secondary supernumerary data resource through an overlay window in the addressable memory space of primary main array memory. Memory accesses (e.g., reads or writes) which specify a memory location which is within the defined address space of the overlay window are redirected to the secondary supernumerary data resource instead of accessing the primary main array memory.

Abstract: System, apparatus, and method to enable and disable a mode of operation of a stacked circuit arrangement on an independent circuit basis using register bits and a single shared mode control line.

Abstract: A technique includes sharing common external terminals of a memory device to communicate data and an address with the memory device for a given memory operation. Different sets of address bits indicative of the address are communicated over the common external terminals at different times.